Updated ALU (Q4) with 7seg and confirmed operation on board

modules/alu.sv

@@ -3,12 +3,14 @@
 
 `include "asu.sv"
 `include "lu.sv"
+`include "seven_seg.sv"
 
 // flags[0:0] = Cout
 // flags[1:1] = Overflow
 module alu #(parameter width=2)(input logic [3:0] op,
     input logic [2**width-1:0] A, input logic [2**width-1:0] B,
-    output logic [2**width-1:0] OUT_1, output logic[1:0] flags);
+    output logic [2**width-1:0] OUT_1, output logic[1:0] flags,
+	 output logic [7:0] out_seg1);
 
     logic [0:0] asu_op;
     logic [2**width-1:0] asu_out;
@@ -33,5 +35,6 @@ module alu #(parameter width=2)(input logic [3:0] op,
             default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
         endcase
     end
+	 seven_seg dut(OUT_1, 1, out_seg1);
 endmodule
 `endif