diff --git a/Quartus/A1_Q4/alu.qsf b/Quartus/A1_Q4/alu.qsf
index 24346c9..2399d70 100644
--- a/Quartus/A1_Q4/alu.qsf
+++ b/Quartus/A1_Q4/alu.qsf
@@ -58,4 +58,52 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_location_assignment PIN_V19 -to out_seg1[1]
+set_location_assignment PIN_V18 -to out_seg1[2]
+set_location_assignment PIN_V17 -to out_seg1[3]
+set_location_assignment PIN_W18 -to out_seg1[4]
+set_location_assignment PIN_Y20 -to out_seg1[5]
+set_location_assignment PIN_Y19 -to out_seg1[6]
+set_location_assignment PIN_Y18 -to out_seg1[7]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg1[1]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg1[2]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg1[3]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg1[4]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg1[5]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg1[6]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg1[7]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to op[0]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to op[1]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to op[2]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to op[3]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to op
+set_instance_assignment -name IO_STANDARD "2.5 V" -to flags[0]
+set_location_assignment PIN_AE19 -to op[3]
+set_location_assignment PIN_Y11 -to op[2]
+set_location_assignment PIN_AC10 -to op[1]
+set_location_assignment PIN_V10 -to op[0]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to B[0]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to B[1]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to B[2]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to B[3]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to B
+set_instance_assignment -name IO_STANDARD "1.2 V" -to A[0]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to A[1]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to A[2]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to A[3]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to A
+set_location_assignment PIN_AC9 -to B[0]
+set_location_assignment PIN_AE10 -to B[1]
+set_location_assignment PIN_AD13 -to B[2]
+set_location_assignment PIN_AC8 -to B[3]
+set_location_assignment PIN_P11 -to A[0]
+set_location_assignment PIN_P12 -to A[1]
+set_location_assignment PIN_Y15 -to A[2]
+set_location_assignment PIN_Y16 -to A[3]
+set_location_assignment PIN_J10 -to flags[1]
+set_location_assignment PIN_H7 -to flags[0]
+set_location_assignment PIN_G7 -to OUT_1[3]
+set_location_assignment PIN_F7 -to OUT_1[0]
+set_location_assignment PIN_F6 -to OUT_1[1]
+set_location_assignment PIN_G6 -to OUT_1[2]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Quartus/A1_Q4/alu.qws b/Quartus/A1_Q4/alu.qws
deleted file mode 100644
index a22a1c5..0000000
Binary files a/Quartus/A1_Q4/alu.qws and /dev/null differ
diff --git a/Quartus/A1_Q4/db/A1_Q4.quiproj.2570.rdr.flock b/Quartus/A1_Q4/db/A1_Q4.quiproj.2570.rdr.flock
new file mode 100644
index 0000000..e69de29
diff --git a/Quartus/A1_Q4/db/alu.(0).cnf.cdb b/Quartus/A1_Q4/db/alu.(0).cnf.cdb
index c3e3f20..0434f01 100644
Binary files a/Quartus/A1_Q4/db/alu.(0).cnf.cdb and b/Quartus/A1_Q4/db/alu.(0).cnf.cdb differ
diff --git a/Quartus/A1_Q4/db/alu.(0).cnf.hdb b/Quartus/A1_Q4/db/alu.(0).cnf.hdb
index 82f6b47..35a95cf 100644
Binary files a/Quartus/A1_Q4/db/alu.(0).cnf.hdb and b/Quartus/A1_Q4/db/alu.(0).cnf.hdb differ
diff --git a/Quartus/A1_Q4/db/alu.(3).cnf.cdb b/Quartus/A1_Q4/db/alu.(3).cnf.cdb
new file mode 100644
index 0000000..b504a79
Binary files /dev/null and b/Quartus/A1_Q4/db/alu.(3).cnf.cdb differ
diff --git a/Quartus/A1_Q4/db/alu.(3).cnf.hdb b/Quartus/A1_Q4/db/alu.(3).cnf.hdb
new file mode 100644
index 0000000..9aa2ea2
Binary files /dev/null and b/Quartus/A1_Q4/db/alu.(3).cnf.hdb differ
diff --git a/Quartus/A1_Q4/db/alu.(4).cnf.cdb b/Quartus/A1_Q4/db/alu.(4).cnf.cdb
new file mode 100644
index 0000000..21cdb29
Binary files /dev/null and b/Quartus/A1_Q4/db/alu.(4).cnf.cdb differ
diff --git a/Quartus/A1_Q4/db/alu.(4).cnf.hdb b/Quartus/A1_Q4/db/alu.(4).cnf.hdb
new file mode 100644
index 0000000..fb96c87
Binary files /dev/null and b/Quartus/A1_Q4/db/alu.(4).cnf.hdb differ
diff --git a/Quartus/A1_Q4/db/alu.(5).cnf.cdb b/Quartus/A1_Q4/db/alu.(5).cnf.cdb
new file mode 100644
index 0000000..e2ec63a
Binary files /dev/null and b/Quartus/A1_Q4/db/alu.(5).cnf.cdb differ
diff --git a/Quartus/A1_Q4/db/alu.(5).cnf.hdb b/Quartus/A1_Q4/db/alu.(5).cnf.hdb
new file mode 100644
index 0000000..d952223
Binary files /dev/null and b/Quartus/A1_Q4/db/alu.(5).cnf.hdb differ
diff --git a/Quartus/A1_Q4/db/alu.(6).cnf.cdb b/Quartus/A1_Q4/db/alu.(6).cnf.cdb
new file mode 100644
index 0000000..e2d3185
Binary files /dev/null and b/Quartus/A1_Q4/db/alu.(6).cnf.cdb differ
diff --git a/Quartus/A1_Q4/db/alu.(6).cnf.hdb b/Quartus/A1_Q4/db/alu.(6).cnf.hdb
new file mode 100644
index 0000000..0179fb6
Binary files /dev/null and b/Quartus/A1_Q4/db/alu.(6).cnf.hdb differ
diff --git a/Quartus/A1_Q4/db/alu.(7).cnf.cdb b/Quartus/A1_Q4/db/alu.(7).cnf.cdb
new file mode 100644
index 0000000..56740be
Binary files /dev/null and b/Quartus/A1_Q4/db/alu.(7).cnf.cdb differ
diff --git a/Quartus/A1_Q4/db/alu.(7).cnf.hdb b/Quartus/A1_Q4/db/alu.(7).cnf.hdb
new file mode 100644
index 0000000..a626f72
Binary files /dev/null and b/Quartus/A1_Q4/db/alu.(7).cnf.hdb differ
diff --git a/Quartus/A1_Q4/db/alu.(8).cnf.cdb b/Quartus/A1_Q4/db/alu.(8).cnf.cdb
new file mode 100644
index 0000000..2075357
Binary files /dev/null and b/Quartus/A1_Q4/db/alu.(8).cnf.cdb differ
diff --git a/Quartus/A1_Q4/db/alu.(8).cnf.hdb b/Quartus/A1_Q4/db/alu.(8).cnf.hdb
new file mode 100644
index 0000000..f9b9f3d
Binary files /dev/null and b/Quartus/A1_Q4/db/alu.(8).cnf.hdb differ
diff --git a/Quartus/A1_Q4/db/alu.asm.qmsg b/Quartus/A1_Q4/db/alu.asm.qmsg
index f9ebb7d..b372b3c 100644
--- a/Quartus/A1_Q4/db/alu.asm.qmsg
+++ b/Quartus/A1_Q4/db/alu.asm.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430641404 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430641405 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:04:01 2026 " "Processing started: Tue Sep 15 10:04:01 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430641405 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789430641405 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789430641405 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789430642068 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789430646380 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "525 " "Peak virtual memory: 525 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430646577 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:04:06 2026 " "Processing ended: Tue Sep 15 10:04:06 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430646577 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430646577 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430646577 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789430646577 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789462574974 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789462574974 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 18:56:14 2026 " "Processing started: Tue Sep 15 18:56:14 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789462574974 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789462574974 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789462574974 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789462575655 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789462580117 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "514 " "Peak virtual memory: 514 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789462580317 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 18:56:20 2026 " "Processing ended: Tue Sep 15 18:56:20 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789462580317 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789462580317 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789462580317 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789462580317 ""}
diff --git a/Quartus/A1_Q4/db/alu.asm.rdb b/Quartus/A1_Q4/db/alu.asm.rdb
index 7485375..2fc3f48 100644
Binary files a/Quartus/A1_Q4/db/alu.asm.rdb and b/Quartus/A1_Q4/db/alu.asm.rdb differ
diff --git a/Quartus/A1_Q4/db/alu.cmp.bpm b/Quartus/A1_Q4/db/alu.cmp.bpm
index ab43975..a978850 100644
Binary files a/Quartus/A1_Q4/db/alu.cmp.bpm and b/Quartus/A1_Q4/db/alu.cmp.bpm differ
diff --git a/Quartus/A1_Q4/db/alu.cmp.cdb b/Quartus/A1_Q4/db/alu.cmp.cdb
index 4efdde2..9f16c51 100644
Binary files a/Quartus/A1_Q4/db/alu.cmp.cdb and b/Quartus/A1_Q4/db/alu.cmp.cdb differ
diff --git a/Quartus/A1_Q4/db/alu.cmp.hdb b/Quartus/A1_Q4/db/alu.cmp.hdb
index 2ee8e7a..43f6d5f 100644
Binary files a/Quartus/A1_Q4/db/alu.cmp.hdb and b/Quartus/A1_Q4/db/alu.cmp.hdb differ
diff --git a/Quartus/A1_Q4/db/alu.cmp.idb b/Quartus/A1_Q4/db/alu.cmp.idb
index 2b7d7a5..d58bb71 100644
Binary files a/Quartus/A1_Q4/db/alu.cmp.idb and b/Quartus/A1_Q4/db/alu.cmp.idb differ
diff --git a/Quartus/A1_Q4/db/alu.cmp.logdb b/Quartus/A1_Q4/db/alu.cmp.logdb
index 90ff09e..41ea25d 100644
--- a/Quartus/A1_Q4/db/alu.cmp.logdb
+++ b/Quartus/A1_Q4/db/alu.cmp.logdb
@@ -1,11 +1,11 @@
v1
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
@@ -29,30 +29,38 @@ IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
-IO_RULES_MATRIX,Total Pass,0;0;0;0;0;18;0;0;0;0;0;0;0;6;0;0;0;0;6;0;0;0;0;6;0;18;18;0,
+IO_RULES_MATRIX,Total Pass,0;25;25;0;0;26;25;0;0;0;0;0;0;14;0;0;0;0;14;0;0;0;0;14;0;26;26;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,18;18;18;18;18;0;18;18;18;18;18;18;18;12;18;18;18;18;12;18;18;18;18;12;18;0;0;18,
+IO_RULES_MATRIX,Total Inapplicable,26;1;1;26;26;0;1;26;26;26;26;26;26;12;26;26;26;26;12;26;26;26;26;12;26;0;0;26,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,OUT_1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,OUT_1[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,OUT_1[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,OUT_1[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,flags[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,flags[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,op[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,op[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,B[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,A[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,op[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,op[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,B[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,A[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,B[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,A[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,B[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,A[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,OUT_1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,OUT_1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,OUT_1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,OUT_1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,flags[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,flags[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,out_seg1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,out_seg1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,out_seg1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,out_seg1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,out_seg1[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,out_seg1[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,out_seg1[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,out_seg1[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,op[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,op[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,op[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,op[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,B[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,A[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,B[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,A[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,B[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,A[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,B[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,A[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,28,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,19,
diff --git a/Quartus/A1_Q4/db/alu.cmp.rdb b/Quartus/A1_Q4/db/alu.cmp.rdb
index 3fe92a2..6e9028c 100644
Binary files a/Quartus/A1_Q4/db/alu.cmp.rdb and b/Quartus/A1_Q4/db/alu.cmp.rdb differ
diff --git a/Quartus/A1_Q4/db/alu.db_info b/Quartus/A1_Q4/db/alu.db_info
index cfe4bf5..d295424 100644
--- a/Quartus/A1_Q4/db/alu.db_info
+++ b/Quartus/A1_Q4/db/alu.db_info
@@ -1,3 +1,3 @@
Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Version_Index = 604268800
-Creation_Time = Tue Sep 15 10:02:02 2026
+Creation_Time = Tue Sep 15 18:30:17 2026
diff --git a/Quartus/A1_Q4/db/alu.eda.qmsg b/Quartus/A1_Q4/db/alu.eda.qmsg
index 26dde4c..fc7097d 100644
--- a/Quartus/A1_Q4/db/alu.eda.qmsg
+++ b/Quartus/A1_Q4/db/alu.eda.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430654884 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430654884 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:04:14 2026 " "Processing started: Tue Sep 15 10:04:14 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430654884 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430654884 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430654884 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789430655640 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "alu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/ simulation " "Generated file alu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789430655696 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430655731 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:04:15 2026 " "Processing ended: Tue Sep 15 10:04:15 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430655731 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430655731 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430655731 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430655731 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789462588665 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789462588667 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 18:56:28 2026 " "Processing started: Tue Sep 15 18:56:28 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789462588667 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789462588667 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789462588667 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789462589561 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "alu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/ simulation " "Generated file alu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789462589627 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "670 " "Peak virtual memory: 670 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789462589663 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 18:56:29 2026 " "Processing ended: Tue Sep 15 18:56:29 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789462589663 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789462589663 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789462589663 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789462589663 ""}
diff --git a/Quartus/A1_Q4/db/alu.fit.qmsg b/Quartus/A1_Q4/db/alu.fit.qmsg
index 96d1983..cc3a23b 100644
--- a/Quartus/A1_Q4/db/alu.fit.qmsg
+++ b/Quartus/A1_Q4/db/alu.fit.qmsg
@@ -1,44 +1,45 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789430610558 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789430610558 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "alu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"alu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789430610563 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789430610632 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789430610632 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789430611045 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789430611073 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789430611121 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "18 18 " "No exact pin location assignment(s) for 18 pins of 18 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789430611389 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789430617956 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430618032 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789430618036 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789430618036 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789430618037 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789430618037 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789430618038 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789430618038 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789430618038 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789430618038 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789430618038 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430618057 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "alu.sdc " "Synopsys Design Constraints File file not found: 'alu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789430623909 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789430623909 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789430623910 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789430623910 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789430623911 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789430623911 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789430623912 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789430623914 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789430623985 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430626215 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789430627179 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789430627539 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430627539 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789430628497 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11"} { { 12 { 0 ""} 0 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789430634025 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789430634025 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789430634284 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789430634284 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789430634284 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430634286 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789430635157 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789430635194 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789430635550 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789430635550 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789430636274 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430638928 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1388 " "Peak virtual memory: 1388 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430639787 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:03:59 2026 " "Processing ended: Tue Sep 15 10:03:59 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430639787 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430639787 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430639787 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789430639787 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789462544992 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789462544993 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "alu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"alu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789462544998 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789462545065 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789462545065 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789462545481 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789462545509 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789462545558 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 26 " "No exact pin location assignment(s) for 1 pins of 26 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789462545815 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789462552513 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789462552568 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789462552570 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789462552571 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789462552571 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789462552571 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789462552571 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789462552572 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789462552572 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789462552572 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789462552572 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789462552602 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "alu.sdc " "Synopsys Design Constraints File file not found: 'alu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789462558630 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789462558630 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789462558631 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789462558631 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789462558632 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789462558632 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789462558633 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789462558636 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789462558743 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789462559594 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789462560341 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789462560659 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789462560660 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789462561254 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X33_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X33_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X33_Y11"} { { 12 { 0 ""} 23 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789462566887 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789462566887 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789462567156 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789462567156 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789462567156 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789462567159 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789462568536 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789462568572 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789462568988 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789462568988 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789462569591 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789462572530 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1789462572797 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1341 " "Peak virtual memory: 1341 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789462573375 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 18:56:13 2026 " "Processing ended: Tue Sep 15 18:56:13 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789462573375 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:29 " "Elapsed time: 00:00:29" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789462573375 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:41 " "Total CPU time (on all processors): 00:00:41" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789462573375 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789462573375 ""}
diff --git a/Quartus/A1_Q4/db/alu.hier_info b/Quartus/A1_Q4/db/alu.hier_info
index 3347177..27e08f0 100644
--- a/Quartus/A1_Q4/db/alu.hier_info
+++ b/Quartus/A1_Q4/db/alu.hier_info
@@ -17,12 +17,20 @@ B[0] => B[0].IN2
B[1] => B[1].IN2
B[2] => B[2].IN2
B[3] => B[3].IN2
-OUT_1[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
-OUT_1[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
-OUT_1[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
-OUT_1[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
-flags[0] <= asu:adder_unit.port4
-flags[1] <= asu:adder_unit.port5
+OUT_1[0] << OUT_1[0].DB_MAX_OUTPUT_PORT_TYPE
+OUT_1[1] << OUT_1[1].DB_MAX_OUTPUT_PORT_TYPE
+OUT_1[2] << OUT_1[2].DB_MAX_OUTPUT_PORT_TYPE
+OUT_1[3] << OUT_1[3].DB_MAX_OUTPUT_PORT_TYPE
+flags[0] << asu:adder_unit.port4
+flags[1] << asu:adder_unit.port5
+out_seg1[0] << seven_seg:dut.port2
+out_seg1[1] << seven_seg:dut.port2
+out_seg1[2] << seven_seg:dut.port2
+out_seg1[3] << seven_seg:dut.port2
+out_seg1[4] << seven_seg:dut.port2
+out_seg1[5] << seven_seg:dut.port2
+out_seg1[6] << seven_seg:dut.port2
+out_seg1[7] << seven_seg:dut.port2
|alu|asu:adder_unit
@@ -91,3 +99,49 @@ Y[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
Y[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
+|alu|seven_seg:dut
+num[0] => Decoder0.IN3
+num[0] => Mux0.IN19
+num[0] => Mux1.IN19
+num[0] => Mux2.IN19
+num[0] => Mux3.IN19
+num[0] => Mux4.IN19
+num[0] => Mux5.IN19
+num[1] => Decoder0.IN2
+num[1] => Mux0.IN18
+num[1] => Mux1.IN18
+num[1] => Mux2.IN18
+num[1] => Mux3.IN18
+num[1] => Mux4.IN18
+num[1] => Mux5.IN18
+num[2] => Decoder0.IN1
+num[2] => Mux0.IN17
+num[2] => Mux1.IN17
+num[2] => Mux2.IN17
+num[2] => Mux3.IN17
+num[2] => Mux4.IN17
+num[2] => Mux5.IN17
+num[3] => Decoder0.IN0
+num[3] => Mux0.IN16
+num[3] => Mux1.IN16
+num[3] => Mux2.IN16
+num[3] => Mux3.IN16
+num[3] => Mux4.IN16
+num[3] => Mux5.IN16
+rbi_inv[0] => Mux0.IN15
+rbi_inv[0] => Mux1.IN15
+rbi_inv[0] => Mux2.IN15
+rbi_inv[0] => Mux3.IN15
+rbi_inv[0] => Mux4.IN15
+rbi_inv[0] => Mux5.IN15
+rbi_inv[0] => segments.DATAB
+segments[0] <= segments.DB_MAX_OUTPUT_PORT_TYPE
+segments[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
+segments[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
+segments[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
+segments[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
+segments[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
+segments[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
+segments[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/Quartus/A1_Q4/db/alu.hif b/Quartus/A1_Q4/db/alu.hif
index 35355a7..bfeb875 100644
Binary files a/Quartus/A1_Q4/db/alu.hif and b/Quartus/A1_Q4/db/alu.hif differ
diff --git a/Quartus/A1_Q4/db/alu.lpc.html b/Quartus/A1_Q4/db/alu.lpc.html
index 54e44cd..41614fc 100644
--- a/Quartus/A1_Q4/db/alu.lpc.html
+++ b/Quartus/A1_Q4/db/alu.lpc.html
@@ -16,6 +16,22 @@
| Output only Bidir |
+| dut |
+5 |
+1 |
+0 |
+1 |
+8 |
+1 |
+1 |
+1 |
+0 |
+0 |
+0 |
+0 |
+0 |
+
+
| logic_unit |
10 |
0 |
diff --git a/Quartus/A1_Q4/db/alu.lpc.rdb b/Quartus/A1_Q4/db/alu.lpc.rdb
index 8be49ac..e0110b0 100644
Binary files a/Quartus/A1_Q4/db/alu.lpc.rdb and b/Quartus/A1_Q4/db/alu.lpc.rdb differ
diff --git a/Quartus/A1_Q4/db/alu.lpc.txt b/Quartus/A1_Q4/db/alu.lpc.txt
index fc26869..5c1c8fe 100644
--- a/Quartus/A1_Q4/db/alu.lpc.txt
+++ b/Quartus/A1_Q4/db/alu.lpc.txt
@@ -3,6 +3,7 @@
+------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; dut ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; logic_unit ; 10 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; adder_unit ; 9 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/Quartus/A1_Q4/db/alu.map.bpm b/Quartus/A1_Q4/db/alu.map.bpm
index afe79d4..d8d6fce 100644
Binary files a/Quartus/A1_Q4/db/alu.map.bpm and b/Quartus/A1_Q4/db/alu.map.bpm differ
diff --git a/Quartus/A1_Q4/db/alu.map.cdb b/Quartus/A1_Q4/db/alu.map.cdb
index 0c6fd07..164506a 100644
Binary files a/Quartus/A1_Q4/db/alu.map.cdb and b/Quartus/A1_Q4/db/alu.map.cdb differ
diff --git a/Quartus/A1_Q4/db/alu.map.hdb b/Quartus/A1_Q4/db/alu.map.hdb
index dabf3b0..9d8040b 100644
Binary files a/Quartus/A1_Q4/db/alu.map.hdb and b/Quartus/A1_Q4/db/alu.map.hdb differ
diff --git a/Quartus/A1_Q4/db/alu.map.qmsg b/Quartus/A1_Q4/db/alu.map.qmsg
index 195bfba..5dbf63d 100644
--- a/Quartus/A1_Q4/db/alu.map.qmsg
+++ b/Quartus/A1_Q4/db/alu.map.qmsg
@@ -1,13 +1,16 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430597214 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430597215 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:03:17 2026 " "Processing started: Tue Sep 15 10:03:17 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430597215 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430597215 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430597215 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789430597568 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789430597568 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv 3 3 " "Found 3 design units, including 3 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 asu " "Found entity 1: asu" { } { { "asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789430607470 ""} { "Info" "ISGN_ENTITY_NAME" "2 lu " "Found entity 2: lu" { } { { "lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789430607470 ""} { "Info" "ISGN_ENTITY_NAME" "3 alu " "Found entity 3: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789430607470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430607470 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "alu " "Elaborating entity \"alu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789430607626 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 16 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789430607634 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 19 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789430607639 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789430608371 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789430608734 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789430608734 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "32 " "Implemented 32 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789430608768 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789430608768 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789430608768 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789430608768 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430608774 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:03:28 2026 " "Processing ended: Tue Sep 15 10:03:28 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430608774 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430608774 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430608774 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430608774 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789462532323 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789462532324 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 18:55:32 2026 " "Processing started: Tue Sep 15 18:55:32 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789462532324 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789462532324 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789462532324 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789462532647 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789462532648 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv 4 4 " "Found 4 design units, including 4 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 asu " "Found entity 1: asu" { } { { "asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789462541942 ""} { "Info" "ISGN_ENTITY_NAME" "2 lu " "Found entity 2: lu" { } { { "lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789462541942 ""} { "Info" "ISGN_ENTITY_NAME" "3 seven_seg " "Found entity 3: seven_seg" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789462541942 ""} { "Info" "ISGN_ENTITY_NAME" "4 alu " "Found entity 4: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 10 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789462541942 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789462541942 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "alu " "Elaborating entity \"alu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789462542081 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789462542084 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789462542090 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg:dut " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg:dut\"" { } { { "../../modules/alu.sv" "dut" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 38 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789462542094 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1789462542681 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg1\[0\] GND " "Pin \"out_seg1\[0\]\" is stuck at GND" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 13 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1789462542713 "|alu|out_seg1[0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1789462542713 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789462542828 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789462543187 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789462543187 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "47 " "Implemented 47 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789462543220 ""} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Implemented 14 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789462543220 ""} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Implemented 21 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789462543220 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789462543220 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "439 " "Peak virtual memory: 439 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789462543227 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 18:55:43 2026 " "Processing ended: Tue Sep 15 18:55:43 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789462543227 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789462543227 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789462543227 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789462543227 ""}
diff --git a/Quartus/A1_Q4/db/alu.map.rdb b/Quartus/A1_Q4/db/alu.map.rdb
index c52b0d6..7e8cd4f 100644
Binary files a/Quartus/A1_Q4/db/alu.map.rdb and b/Quartus/A1_Q4/db/alu.map.rdb differ
diff --git a/Quartus/A1_Q4/db/alu.map_bb.cdb b/Quartus/A1_Q4/db/alu.map_bb.cdb
index 2f0bb40..c37d6c0 100644
Binary files a/Quartus/A1_Q4/db/alu.map_bb.cdb and b/Quartus/A1_Q4/db/alu.map_bb.cdb differ
diff --git a/Quartus/A1_Q4/db/alu.map_bb.hdb b/Quartus/A1_Q4/db/alu.map_bb.hdb
index 2dd3372..1e8db55 100644
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diff --git a/Quartus/A1_Q4/db/alu.pplq.rdb b/Quartus/A1_Q4/db/alu.pplq.rdb
new file mode 100644
index 0000000..46c284e
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diff --git a/Quartus/A1_Q4/db/alu.pre_map.hdb b/Quartus/A1_Q4/db/alu.pre_map.hdb
index 432e0ae..61e8858 100644
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diff --git a/Quartus/A1_Q4/db/alu.routing.rdb b/Quartus/A1_Q4/db/alu.routing.rdb
index 8563023..6a17d05 100644
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diff --git a/Quartus/A1_Q4/db/alu.rtlv.hdb b/Quartus/A1_Q4/db/alu.rtlv.hdb
index d20d1b9..8e95759 100644
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diff --git a/Quartus/A1_Q4/db/alu.rtlv_sg.cdb b/Quartus/A1_Q4/db/alu.rtlv_sg.cdb
index 1751db9..e1474b7 100644
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diff --git a/Quartus/A1_Q4/db/alu.rtlv_sg_swap.cdb b/Quartus/A1_Q4/db/alu.rtlv_sg_swap.cdb
index a00be8b..cd60be2 100644
Binary files a/Quartus/A1_Q4/db/alu.rtlv_sg_swap.cdb and b/Quartus/A1_Q4/db/alu.rtlv_sg_swap.cdb differ
diff --git a/Quartus/A1_Q4/db/alu.sta.qmsg b/Quartus/A1_Q4/db/alu.sta.qmsg
index f1ffb8f..866d86e 100644
--- a/Quartus/A1_Q4/db/alu.sta.qmsg
+++ b/Quartus/A1_Q4/db/alu.sta.qmsg
@@ -1,61 +1,61 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430648073 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430648073 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:04:07 2026 " "Processing started: Tue Sep 15 10:04:07 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430648073 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430648073 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q4 -c alu " "Command: quartus_sta A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430648073 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789430648128 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789430648621 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789430648622 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430648694 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430648694 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "alu.sdc " "Synopsys Design Constraints File file not found: 'alu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789430649270 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430649271 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430649271 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430649272 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430649272 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430649272 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789430649273 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789430649277 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430649278 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649279 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649282 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649283 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649284 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649285 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649285 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430649287 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430649326 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430650655 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430650741 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430650741 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430650741 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430650742 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650743 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650745 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650746 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650747 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650748 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650748 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430650750 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430651010 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430651713 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430651764 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430651764 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430651764 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430651764 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651765 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651766 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651767 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651768 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651769 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430651771 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430651921 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430651921 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430651922 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430651922 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651923 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651924 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651925 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651925 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651926 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430653319 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430653319 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "793 " "Peak virtual memory: 793 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430653351 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:04:13 2026 " "Processing ended: Tue Sep 15 10:04:13 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430653351 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430653351 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430653351 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789430653351 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789462581803 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789462581804 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 18:56:21 2026 " "Processing started: Tue Sep 15 18:56:21 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789462581804 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789462581804 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q4 -c alu " "Command: quartus_sta A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789462581804 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789462581858 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789462582335 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789462582335 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789462582408 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789462582408 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "alu.sdc " "Synopsys Design Constraints File file not found: 'alu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789462582987 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789462582988 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789462582988 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789462582988 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789462582989 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789462582989 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789462582990 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789462582994 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789462582995 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462582996 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462583002 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462583003 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462583004 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462583005 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462583005 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789462583008 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789462583047 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789462584014 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789462584105 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789462584106 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789462584106 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789462584106 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462584107 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462584108 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462584109 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462584110 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462584111 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462584112 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789462584113 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789462584360 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789462584929 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789462584974 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789462584974 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789462584975 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789462584975 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462584976 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462584977 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462584978 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462584978 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462584979 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789462584981 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789462585135 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789462585135 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789462585135 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789462585136 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462585137 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462585138 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462585139 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462585139 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789462585140 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789462586676 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789462586677 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "765 " "Peak virtual memory: 765 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789462586717 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 18:56:26 2026 " "Processing ended: Tue Sep 15 18:56:26 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789462586717 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789462586717 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789462586717 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789462586717 ""}
diff --git a/Quartus/A1_Q4/db/alu.sta.rdb b/Quartus/A1_Q4/db/alu.sta.rdb
index 13ba4f0..bfdb558 100644
Binary files a/Quartus/A1_Q4/db/alu.sta.rdb and b/Quartus/A1_Q4/db/alu.sta.rdb differ
diff --git a/Quartus/A1_Q4/db/alu.sta_cmp.7_H6_slow_1100mv_85c.tdb b/Quartus/A1_Q4/db/alu.sta_cmp.7_H6_slow_1100mv_85c.tdb
index 3f3ac2e..d419434 100644
Binary files a/Quartus/A1_Q4/db/alu.sta_cmp.7_H6_slow_1100mv_85c.tdb and b/Quartus/A1_Q4/db/alu.sta_cmp.7_H6_slow_1100mv_85c.tdb differ
diff --git a/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_0c.ddb b/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_0c.ddb
index 72ed6fb..150c68f 100644
Binary files a/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_0c.ddb and b/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_0c.ddb differ
diff --git a/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_85c.ddb b/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_85c.ddb
index c620d14..9ba4493 100644
Binary files a/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_85c.ddb and b/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_85c.ddb differ
diff --git a/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_0c.ddb b/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_0c.ddb
index c898c33..818c9b8 100644
Binary files a/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_0c.ddb and b/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_0c.ddb differ
diff --git a/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_85c.ddb b/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_85c.ddb
index 63da1ab..20530ca 100644
Binary files a/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_85c.ddb and b/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_85c.ddb differ
diff --git a/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_0c.ddb b/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_0c.ddb
index 61dedea..2d94766 100644
Binary files a/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_0c.ddb and b/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_0c.ddb differ
diff --git a/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_85c.ddb b/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_85c.ddb
index 9f80f5b..b99d1dd 100644
Binary files a/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_85c.ddb and b/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_85c.ddb differ
diff --git a/Quartus/A1_Q4/db/alu.tmw_info b/Quartus/A1_Q4/db/alu.tmw_info
index 52c26ab..96c3101 100644
--- a/Quartus/A1_Q4/db/alu.tmw_info
+++ b/Quartus/A1_Q4/db/alu.tmw_info
@@ -1,7 +1,7 @@
-start_full_compilation:s:00:01:00
-start_analysis_synthesis:s:00:00:13-start_full_compilation
+start_full_compilation:s:00:00:59
+start_analysis_synthesis:s:00:00:12-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:31-start_full_compilation
-start_assembler:s:00:00:07-start_full_compilation
+start_assembler:s:00:00:06-start_full_compilation
start_timing_analyzer:s:00:00:07-start_full_compilation
-start_eda_netlist_writer:s:00:00:02-start_full_compilation
+start_eda_netlist_writer:s:00:00:03-start_full_compilation
diff --git a/Quartus/A1_Q4/db/alu.vpr.ammdb b/Quartus/A1_Q4/db/alu.vpr.ammdb
index 01b2d8a..3838486 100644
Binary files a/Quartus/A1_Q4/db/alu.vpr.ammdb and b/Quartus/A1_Q4/db/alu.vpr.ammdb differ
diff --git a/Quartus/A1_Q4/db/alu_partition_pins.json b/Quartus/A1_Q4/db/alu_partition_pins.json
index 2ca2efe..aafdb28 100644
--- a/Quartus/A1_Q4/db/alu_partition_pins.json
+++ b/Quartus/A1_Q4/db/alu_partition_pins.json
@@ -27,6 +27,34 @@
"name" : "flags[1]",
"strict" : false
},
+ {
+ "name" : "out_seg1[1]",
+ "strict" : false
+ },
+ {
+ "name" : "out_seg1[2]",
+ "strict" : false
+ },
+ {
+ "name" : "out_seg1[3]",
+ "strict" : false
+ },
+ {
+ "name" : "out_seg1[4]",
+ "strict" : false
+ },
+ {
+ "name" : "out_seg1[5]",
+ "strict" : false
+ },
+ {
+ "name" : "out_seg1[6]",
+ "strict" : false
+ },
+ {
+ "name" : "out_seg1[7]",
+ "strict" : false
+ },
{
"name" : "op[2]",
"strict" : false
@@ -35,14 +63,6 @@
"name" : "op[3]",
"strict" : false
},
- {
- "name" : "B[0]",
- "strict" : false
- },
- {
- "name" : "A[0]",
- "strict" : false
- },
{
"name" : "op[0]",
"strict" : false
@@ -59,6 +79,14 @@
"name" : "A[3]",
"strict" : false
},
+ {
+ "name" : "B[0]",
+ "strict" : false
+ },
+ {
+ "name" : "A[0]",
+ "strict" : false
+ },
{
"name" : "B[1]",
"strict" : false
diff --git a/Quartus/A1_Q4/db/prev_cmp_A1_Q4.qmsg b/Quartus/A1_Q4/db/prev_cmp_A1_Q4.qmsg
index 5da9be4..8af21d5 100644
--- a/Quartus/A1_Q4/db/prev_cmp_A1_Q4.qmsg
+++ b/Quartus/A1_Q4/db/prev_cmp_A1_Q4.qmsg
@@ -1,10 +1,141 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788927612258 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788927612259 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:20:12 2026 " "Processing started: Wed Sep 9 14:20:12 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788927612259 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927612259 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927612260 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788927612565 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788927612565 ""}
-{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\".\"; expecting \")\" alu.sv(7) " "Verilog HDL syntax error at alu.sv(7) near text: \".\"; expecting \")\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1788927621534 ""}
-{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "alu alu.sv(6) " "Ignored design unit \"alu\" at alu.sv(6) due to previous errors" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 6 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1788927621535 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927621535 ""}
-{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "400 " "Peak virtual memory: 400 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927621575 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Sep 9 14:20:21 2026 " "Processing ended: Wed Sep 9 14:20:21 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927621575 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927621575 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927621575 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927621575 ""}
-{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 1 " "Quartus Prime Full Compilation was unsuccessful. 4 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927622220 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789461937886 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789461937892 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 18:45:37 2026 " "Processing started: Tue Sep 15 18:45:37 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789461937892 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789461937892 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789461937893 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789461938211 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789461938211 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv 4 4 " "Found 4 design units, including 4 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 asu " "Found entity 1: asu" { } { { "asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789461948167 ""} { "Info" "ISGN_ENTITY_NAME" "2 lu " "Found entity 2: lu" { } { { "lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789461948167 ""} { "Info" "ISGN_ENTITY_NAME" "3 seven_seg " "Found entity 3: seven_seg" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789461948167 ""} { "Info" "ISGN_ENTITY_NAME" "4 alu " "Found entity 4: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 10 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789461948167 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789461948167 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "alu " "Elaborating entity \"alu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789461948326 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789461948361 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789461948368 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg:dut " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg:dut\"" { } { { "../../modules/alu.sv" "dut" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 38 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789461948371 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1789461949024 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg1\[0\] GND " "Pin \"out_seg1\[0\]\" is stuck at GND" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 13 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1789461949067 "|alu|out_seg1[0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1789461949067 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789461949198 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789461949620 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789461949620 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "47 " "Implemented 47 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789461949742 ""} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Implemented 14 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789461949742 ""} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Implemented 21 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789461949742 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789461949742 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789461949748 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 18:45:49 2026 " "Processing ended: Tue Sep 15 18:45:49 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789461949748 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789461949748 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789461949748 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789461949748 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1789461951410 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789461951410 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 18:45:50 2026 " "Processing started: Tue Sep 15 18:45:50 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789461951410 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1789461951410 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off A1_Q4 -c alu " "Command: quartus_fit --read_settings_files=off --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1789461951410 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1789461951682 ""}
+{ "Info" "0" "" "Project = A1_Q4" { } { } 0 0 "Project = A1_Q4" 0 0 "Fitter" 0 0 1789461951683 ""}
+{ "Info" "0" "" "Revision = alu" { } { } 0 0 "Revision = alu" 0 0 "Fitter" 0 0 1789461951683 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789461951883 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789461951883 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "alu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"alu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789461951889 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789461951971 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789461951971 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789461952389 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789461952434 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789461952580 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "26 26 " "No exact pin location assignment(s) for 26 pins of 26 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789461952857 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789461959631 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789461959745 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789461959763 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789461959764 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789461959765 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789461959765 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789461959765 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789461959765 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789461959765 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789461959765 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789461959765 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789461959787 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "alu.sdc " "Synopsys Design Constraints File file not found: 'alu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789461965922 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789461965922 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789461965923 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789461965924 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789461965925 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789461965926 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789461965926 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789461965930 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789461966000 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789461967624 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789461968674 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789461969020 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789461969020 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789461969626 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11"} { { 12 { 0 ""} 0 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789461975150 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789461975150 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789461975404 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789461975404 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789461975404 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789461975406 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789461976637 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789461976670 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789461977076 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789461977076 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789461977674 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789461980458 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1343 " "Peak virtual memory: 1343 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789461981321 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 18:46:21 2026 " "Processing ended: Tue Sep 15 18:46:21 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789461981321 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:31 " "Elapsed time: 00:00:31" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789461981321 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:42 " "Total CPU time (on all processors): 00:00:42" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789461981321 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789461981321 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1789461983158 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789461983159 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 18:46:22 2026 " "Processing started: Tue Sep 15 18:46:22 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789461983159 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789461983159 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789461983159 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789461983824 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789461988645 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "518 " "Peak virtual memory: 518 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789461988871 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 18:46:28 2026 " "Processing ended: Tue Sep 15 18:46:28 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789461988871 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789461988871 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789461988871 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789461988871 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1789461989726 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1789461990546 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789461990547 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 18:46:30 2026 " "Processing started: Tue Sep 15 18:46:30 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789461990547 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789461990547 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q4 -c alu " "Command: quartus_sta A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789461990547 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789461990612 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789461991096 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789461991097 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789461991166 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789461991166 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "alu.sdc " "Synopsys Design Constraints File file not found: 'alu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789461991755 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789461991755 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789461991756 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789461991756 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789461991756 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789461991757 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789461991757 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789461991762 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789461991762 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461991763 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461991768 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461991769 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461991770 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461991771 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461991771 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789461991773 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789461991826 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789461992804 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789461992904 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789461992904 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789461992904 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789461992904 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461992905 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461992907 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461992908 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461992909 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461992910 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461992910 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789461992912 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789461993166 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789461993731 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789461993775 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789461993775 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789461993776 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789461993776 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461993777 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461993778 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461993779 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461993779 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461993780 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789461993782 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789461993936 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789461993936 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789461993936 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789461993937 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461993938 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461993938 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461993939 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461993940 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789461993940 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789461995435 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789461995436 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "761 " "Peak virtual memory: 761 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789461995459 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 18:46:35 2026 " "Processing ended: Tue Sep 15 18:46:35 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789461995459 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789461995459 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789461995459 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789461995459 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1789461997111 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789461997111 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 18:46:36 2026 " "Processing started: Tue Sep 15 18:46:36 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789461997111 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789461997111 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789461997111 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789461997858 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "alu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/ simulation " "Generated file alu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789461997939 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789461997971 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 18:46:37 2026 " "Processing ended: Tue Sep 15 18:46:37 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789461997971 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789461997971 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789461997971 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789461997971 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 18 s " "Quartus Prime Full Compilation was successful. 0 errors, 18 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789461998632 ""}
diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.ammdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.ammdb
index 12efe70..569673d 100644
Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.ammdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.ammdb differ
diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.cdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.cdb
index ed82a2b..8039175 100644
Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.cdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.cdb differ
diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.cdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.cdb
index 9e302a7..3eb1e13 100644
Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.cdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.cdb differ
diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.hdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.hdb
index cf2566b..3eff482 100644
Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.hdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.hdb differ
diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hdb
index f6b4768..5e26397 100644
Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hdb differ
diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.rcfdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.rcfdb
index 7ed45bb..3752800 100644
Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.rcfdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.rcfdb differ
diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.cdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.cdb
index 27ef4ce..1cfa513 100644
Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.cdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.cdb differ
diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.dpi b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.dpi
index c2b027c..f77ec28 100644
Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.dpi and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.dpi differ
diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.cdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.cdb
index 82103e9..5ead64c 100644
Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.cdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.cdb differ
diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.hdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.hdb
index 9135c59..142c230 100644
Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.hdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.hdb differ
diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hdb
index dc7f779..ce299a6 100644
Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hdb differ
diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.rrp.hdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.rrp.hdb
index a12ec8a..e86ad73 100644
Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.rrp.hdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.rrp.hdb differ
diff --git a/Quartus/A1_Q4/output_files/alu.asm.rpt b/Quartus/A1_Q4/output_files/alu.asm.rpt
index 8edea52..c7936e0 100644
--- a/Quartus/A1_Q4/output_files/alu.asm.rpt
+++ b/Quartus/A1_Q4/output_files/alu.asm.rpt
@@ -1,5 +1,5 @@
Assembler report for alu
-Tue Sep 15 10:04:06 2026
+Tue Sep 15 18:56:20 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -38,7 +38,7 @@ on the Quartus Prime software download page.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Tue Sep 15 10:04:06 2026 ;
+; Assembler Status ; Successful - Tue Sep 15 18:56:20 2026 ;
; Revision Name ; alu ;
; Top-level Entity Name ; alu ;
; Family ; Cyclone V ;
@@ -67,8 +67,8 @@ on the Quartus Prime software download page.
+----------------+------------------+
; Option ; Setting ;
+----------------+------------------+
-; JTAG usercode ; 0x0078346C ;
-; Checksum ; 0x0078346C ;
+; JTAG usercode ; 0x0078906F ;
+; Checksum ; 0x0078906F ;
+----------------+------------------+
@@ -78,14 +78,14 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
- Info: Processing started: Tue Sep 15 10:04:01 2026
+ Info: Processing started: Tue Sep 15 18:56:14 2026
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 525 megabytes
- Info: Processing ended: Tue Sep 15 10:04:06 2026
- Info: Elapsed time: 00:00:05
+ Info: Peak virtual memory: 514 megabytes
+ Info: Processing ended: Tue Sep 15 18:56:20 2026
+ Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:05
diff --git a/Quartus/A1_Q4/output_files/alu.done b/Quartus/A1_Q4/output_files/alu.done
index 31fd0b2..df116a1 100644
--- a/Quartus/A1_Q4/output_files/alu.done
+++ b/Quartus/A1_Q4/output_files/alu.done
@@ -1 +1 @@
-Tue Sep 15 10:04:16 2026
+Tue Sep 15 18:56:30 2026
diff --git a/Quartus/A1_Q4/output_files/alu.eda.rpt b/Quartus/A1_Q4/output_files/alu.eda.rpt
index a666823..feb1072 100644
--- a/Quartus/A1_Q4/output_files/alu.eda.rpt
+++ b/Quartus/A1_Q4/output_files/alu.eda.rpt
@@ -1,5 +1,5 @@
EDA Netlist Writer report for alu
-Tue Sep 15 10:04:15 2026
+Tue Sep 15 18:56:29 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -37,7 +37,7 @@ on the Quartus Prime software download page.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Tue Sep 15 10:04:15 2026 ;
+; EDA Netlist Writer Status ; Successful - Tue Sep 15 18:56:29 2026 ;
; Revision Name ; alu ;
; Top-level Entity Name ; alu ;
; Family ; Cyclone V ;
@@ -81,13 +81,13 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
- Info: Processing started: Tue Sep 15 10:04:14 2026
+ Info: Processing started: Tue Sep 15 18:56:28 2026
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file alu.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 658 megabytes
- Info: Processing ended: Tue Sep 15 10:04:15 2026
+ Info: Peak virtual memory: 670 megabytes
+ Info: Processing ended: Tue Sep 15 18:56:29 2026
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
diff --git a/Quartus/A1_Q4/output_files/alu.fit.rpt b/Quartus/A1_Q4/output_files/alu.fit.rpt
index a20f98a..a516dd2 100644
--- a/Quartus/A1_Q4/output_files/alu.fit.rpt
+++ b/Quartus/A1_Q4/output_files/alu.fit.rpt
@@ -1,5 +1,5 @@
Fitter report for alu
-Tue Sep 15 10:03:59 2026
+Tue Sep 15 18:56:12 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -10,27 +10,28 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
2. Fitter Summary
3. Fitter Settings
4. Parallel Compilation
- 5. Incremental Compilation Preservation Summary
- 6. Incremental Compilation Partition Settings
- 7. Incremental Compilation Placement Preservation
- 8. Pin-Out File
- 9. Fitter Resource Usage Summary
- 10. Fitter Partition Statistics
- 11. Input Pins
- 12. Output Pins
- 13. I/O Bank Usage
- 14. All Package Pins
- 15. I/O Assignment Warnings
- 16. Fitter Resource Utilization by Entity
- 17. Delay Chain Summary
- 18. Pad To Core Delay Chain Fanout
- 19. Routing Usage Summary
- 20. I/O Rules Summary
- 21. I/O Rules Details
- 22. I/O Rules Matrix
- 23. Fitter Device Options
- 24. Operating Settings and Conditions
- 25. Fitter Messages
+ 5. Ignored Assignments
+ 6. Incremental Compilation Preservation Summary
+ 7. Incremental Compilation Partition Settings
+ 8. Incremental Compilation Placement Preservation
+ 9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. I/O Bank Usage
+ 15. All Package Pins
+ 16. I/O Assignment Warnings
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Routing Usage Summary
+ 21. I/O Rules Summary
+ 22. I/O Rules Details
+ 23. I/O Rules Matrix
+ 24. Fitter Device Options
+ 25. Operating Settings and Conditions
+ 26. Fitter Messages
@@ -57,16 +58,16 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------------+-------------------------------------------------+
-; Fitter Status ; Successful - Tue Sep 15 10:03:59 2026 ;
+; Fitter Status ; Successful - Tue Sep 15 18:56:12 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; alu ;
; Top-level Entity Name ; alu ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
-; Logic utilization (in ALMs) ; 11 / 29,080 ( < 1 % ) ;
+; Logic utilization (in ALMs) ; 14 / 29,080 ( < 1 % ) ;
; Total registers ; 0 ;
-; Total pins ; 18 / 364 ( 5 % ) ;
+; Total pins ; 26 / 364 ( 7 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
; Total RAM Blocks ; 0 / 446 ( 0 % ) ;
@@ -152,18 +153,29 @@ on the Quartus Prime software download page.
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.2% ;
+; Processor 2 ; 0.4% ;
+----------------------------+-------------+
++--------------------------------------------------------------------------------------------+
+; Ignored Assignments ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; I/O Standard ; alu ; ; A ; 1.2 V ; QSF Assignment ;
+; I/O Standard ; alu ; ; B ; 1.2 V ; QSF Assignment ;
+; I/O Standard ; alu ; ; op ; 1.2 V ; QSF Assignment ;
++--------------+----------------+--------------+------------+---------------+----------------+
+
+
+-------------------------------------------------------------------------------------------------+
; Incremental Compilation Preservation Summary ;
+---------------------+-------------------+----------------------------+--------------------------+
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
+---------------------+-------------------+----------------------------+--------------------------+
; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 51 ) ; 0.00 % ( 0 / 51 ) ; 0.00 % ( 0 / 51 ) ;
-; -- Achieved ; 0.00 % ( 0 / 51 ) ; 0.00 % ( 0 / 51 ) ; 0.00 % ( 0 / 51 ) ;
+; -- Requested ; 0.00 % ( 0 / 74 ) ; 0.00 % ( 0 / 74 ) ; 0.00 % ( 0 / 74 ) ;
+; -- Achieved ; 0.00 % ( 0 / 74 ) ; 0.00 % ( 0 / 74 ) ; 0.00 % ( 0 / 74 ) ;
; ; ; ; ;
; Routing (by net) ; ; ; ;
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
@@ -186,7 +198,7 @@ on the Quartus Prime software download page.
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 51 ) ; N/A ; Source File ; N/A ; ;
+; Top ; 0.00 % ( 0 / 74 ) ; N/A ; Source File ; N/A ; ;
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
@@ -202,11 +214,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
+-------------------------------------------------------------+--------------------+-------+
; Resource ; Usage ; % ;
+-------------------------------------------------------------+--------------------+-------+
-; Logic utilization (ALMs needed / total ALMs on device) ; 11 / 29,080 ; < 1 % ;
-; ALMs needed [=A-B+C] ; 11 ; ;
-; [A] ALMs used in final placement [=a+b+c+d] ; 11 / 29,080 ; < 1 % ;
+; Logic utilization (ALMs needed / total ALMs on device) ; 14 / 29,080 ; < 1 % ;
+; ALMs needed [=A-B+C] ; 14 ; ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 14 / 29,080 ; < 1 % ;
; [a] ALMs used for LUT logic and registers ; 0 ; ;
-; [b] ALMs used for LUT logic ; 11 ; ;
+; [b] ALMs used for LUT logic ; 14 ; ;
; [c] ALMs used for registers ; 0 ; ;
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29,080 ; 0 % ;
@@ -218,15 +230,15 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; ; ; ;
; Difficulty packing design ; Low ; ;
; ; ; ;
-; Total LABs: partially or completely used ; 3 / 2,908 ; < 1 % ;
-; -- Logic LABs ; 3 ; ;
+; Total LABs: partially or completely used ; 4 / 2,908 ; < 1 % ;
+; -- Logic LABs ; 4 ; ;
; -- Memory LABs (up to half of total LABs) ; 0 ; ;
; ; ; ;
-; Combinational ALUT usage for logic ; 15 ; ;
+; Combinational ALUT usage for logic ; 22 ; ;
; -- 7 input functions ; 3 ; ;
; -- 6 input functions ; 3 ; ;
; -- 5 input functions ; 0 ; ;
-; -- 4 input functions ; 1 ; ;
+; -- 4 input functions ; 8 ; ;
; -- <=3 input functions ; 8 ; ;
; Combinational ALUT usage for route-throughs ; 0 ; ;
; ; ; ;
@@ -239,8 +251,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; -- Routing optimization registers ; 0 ; ;
; ; ; ;
; Virtual pins ; 0 ; ;
-; I/O pins ; 18 / 364 ; 5 % ;
-; -- Clock pins ; 0 / 14 ; 0 % ;
+; I/O pins ; 26 / 364 ; 7 % ;
+; -- Clock pins ; 2 / 14 ; 14 % ;
; -- Dedicated input pins ; 0 / 23 ; 0 % ;
; ; ; ;
; M10K blocks ; 0 / 446 ; 0 % ;
@@ -270,12 +282,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; Channel PLLs ; 0 / 6 ; 0 % ;
; Impedance control blocks ; 0 / 3 ; 0 % ;
; Hard Memory Controllers ; 0 / 2 ; 0 % ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ;
-; Peak interconnect usage (total/H/V) ; 0.2% / 0.2% / 0.2% ; ;
-; Maximum fan-out ; 7 ; ;
-; Highest non-global fan-out ; 7 ; ;
-; Total fan-out ; 84 ; ;
-; Average fan-out ; 1.65 ; ;
+; Average interconnect usage (total/H/V) ; 0.1% / 0.0% / 0.1% ; ;
+; Peak interconnect usage (total/H/V) ; 0.3% / 0.3% / 0.4% ; ;
+; Maximum fan-out ; 8 ; ;
+; Highest non-global fan-out ; 8 ; ;
+; Total fan-out ; 127 ; ;
+; Average fan-out ; 1.72 ; ;
+-------------------------------------------------------------+--------------------+-------+
@@ -284,11 +296,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
+-------------------------------------------------------------+----------------------+--------------------------------+
; Statistic ; Top ; hard_block:auto_generated_inst ;
+-------------------------------------------------------------+----------------------+--------------------------------+
-; Logic utilization (ALMs needed / total ALMs on device) ; 11 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
-; ALMs needed [=A-B+C] ; 11 ; 0 ;
-; [A] ALMs used in final placement [=a+b+c+d] ; 11 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
+; Logic utilization (ALMs needed / total ALMs on device) ; 14 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
+; ALMs needed [=A-B+C] ; 14 ; 0 ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 14 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
; [a] ALMs used for LUT logic and registers ; 0 ; 0 ;
-; [b] ALMs used for LUT logic ; 11 ; 0 ;
+; [b] ALMs used for LUT logic ; 14 ; 0 ;
; [c] ALMs used for registers ; 0 ; 0 ;
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ;
@@ -300,15 +312,15 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; ; ; ;
; Difficulty packing design ; Low ; Low ;
; ; ; ;
-; Total LABs: partially or completely used ; 3 / 2908 ( < 1 % ) ; 0 / 2908 ( 0 % ) ;
-; -- Logic LABs ; 3 ; 0 ;
+; Total LABs: partially or completely used ; 4 / 2908 ( < 1 % ) ; 0 / 2908 ( 0 % ) ;
+; -- Logic LABs ; 4 ; 0 ;
; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
; ; ; ;
-; Combinational ALUT usage for logic ; 15 ; 0 ;
+; Combinational ALUT usage for logic ; 22 ; 0 ;
; -- 7 input functions ; 3 ; 0 ;
; -- 6 input functions ; 3 ; 0 ;
; -- 5 input functions ; 0 ; 0 ;
-; -- 4 input functions ; 1 ; 0 ;
+; -- 4 input functions ; 8 ; 0 ;
; -- <=3 input functions ; 8 ; 0 ;
; Combinational ALUT usage for route-throughs ; 0 ; 0 ;
; Memory ALUT usage ; 0 ; 0 ;
@@ -325,7 +337,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; ; ; ;
; ; ; ;
; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 18 ; 0 ;
+; I/O pins ; 26 ; 0 ;
; I/O registers ; 0 ; 0 ;
; Total block memory bits ; 0 ; 0 ;
; Total block memory implementation bits ; 0 ; 0 ;
@@ -337,7 +349,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; -- Registered Output Connections ; 0 ; 0 ;
; ; ; ;
; Internal Connections ; ; ;
-; -- Total Connections ; 88 ; 0 ;
+; -- Total Connections ; 131 ; 0 ;
; -- Registered Connections ; 0 ; 0 ;
; ; ; ;
; External Connections ; ; ;
@@ -346,7 +358,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; ; ; ;
; Partition Interface ; ; ;
; -- Input Ports ; 12 ; 0 ;
-; -- Output Ports ; 6 ; 0 ;
+; -- Output Ports ; 14 ; 0 ;
; -- Bidir Ports ; 0 ; 0 ;
; ; ; ;
; Registered Ports ; ; ;
@@ -370,33 +382,41 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; A[0] ; P8 ; 3A ; 7 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; A[1] ; Y11 ; 3B ; 10 ; 0 ; 57 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; A[2] ; R9 ; 3A ; 6 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; A[3] ; Y8 ; 3A ; 6 ; 0 ; 34 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; B[0] ; W11 ; 3B ; 10 ; 0 ; 40 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; B[1] ; AB6 ; 3A ; 4 ; 0 ; 51 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; B[2] ; R8 ; 3A ; 7 ; 0 ; 17 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; B[3] ; R10 ; 3A ; 6 ; 0 ; 17 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; op[0] ; AD6 ; 3A ; 7 ; 0 ; 51 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; op[1] ; U7 ; 3A ; 2 ; 0 ; 91 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; op[2] ; AD7 ; 3A ; 7 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; op[3] ; U9 ; 3B ; 10 ; 0 ; 91 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
+; A[0] ; P11 ; 3B ; 21 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
+; A[1] ; P12 ; 3B ; 21 ; 0 ; 17 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
+; A[2] ; Y15 ; 4A ; 46 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
+; A[3] ; Y16 ; 4A ; 46 ; 0 ; 17 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
+; B[0] ; AC9 ; 3B ; 14 ; 0 ; 34 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
+; B[1] ; AE10 ; 4A ; 36 ; 0 ; 51 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
+; B[2] ; AD13 ; 4A ; 34 ; 0 ; 34 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
+; B[3] ; AC8 ; 3B ; 14 ; 0 ; 51 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
+; op[0] ; V10 ; 3B ; 17 ; 0 ; 74 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
+; op[1] ; AC10 ; 3B ; 12 ; 0 ; 51 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
+; op[2] ; Y11 ; 3B ; 10 ; 0 ; 57 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
+; op[3] ; AE19 ; 4A ; 50 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; OUT_1[0] ; AA6 ; 3A ; 4 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; OUT_1[1] ; Y9 ; 3A ; 4 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; OUT_1[2] ; T9 ; 3B ; 10 ; 0 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; OUT_1[3] ; W8 ; 3A ; 4 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; flags[0] ; AB10 ; 3B ; 12 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; flags[1] ; AA7 ; 3A ; 6 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; OUT_1[0] ; F7 ; 8A ; 14 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; OUT_1[1] ; F6 ; 8A ; 15 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; OUT_1[2] ; G6 ; 8A ; 15 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; OUT_1[3] ; G7 ; 8A ; 14 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; flags[0] ; H7 ; 8A ; 12 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; flags[1] ; J10 ; 8A ; 12 ; 61 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; out_seg1[0] ; M25 ; 6A ; 68 ; 37 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
+; out_seg1[1] ; V19 ; 4A ; 66 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; out_seg1[2] ; V18 ; 4A ; 64 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; out_seg1[3] ; V17 ; 4A ; 64 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; out_seg1[4] ; W18 ; 4A ; 66 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; out_seg1[5] ; Y20 ; 4A ; 65 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; out_seg1[6] ; Y19 ; 4A ; 65 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; out_seg1[7] ; Y18 ; 4A ; 62 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+----------------------------------------------------------------------------+
@@ -406,14 +426,14 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
+----------+------------------+---------------+--------------+---------------+
; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
-; 3A ; 13 / 16 ( 81 % ) ; 2.5V ; -- ; 2.5V ;
-; 3B ; 5 / 32 ( 16 % ) ; 2.5V ; -- ; 2.5V ;
-; 4A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 3B ; 7 / 32 ( 22 % ) ; 1.2V ; -- ; 2.5V ;
+; 4A ; 12 / 80 ( 15 % ) ; 1.2V ; -- ; 2.5V ;
; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 6A ; 1 / 48 ( 2 % ) ; 2.5V ; -- ; 2.5V ;
; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 8A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 8A ; 6 / 32 ( 19 % ) ; 2.5V ; -- ; 2.5V ;
+----------+------------------+---------------+--------------+---------------+
@@ -451,11 +471,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; AA3 ; 14 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ;
; AA4 ; 15 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ;
; AA5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA6 ; 45 ; 3A ; OUT_1[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AA7 ; 47 ; 3A ; flags[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
+; AA6 ; 45 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA7 ; 47 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AA8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AA9 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; AA10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA10 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AA11 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AA12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
; AA13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
@@ -465,7 +485,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; AA17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AA18 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AA19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA20 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AA21 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AA22 ; 170 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; AA23 ; 172 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
@@ -477,14 +497,14 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; AB3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AB4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AB5 ; 33 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AB6 ; 43 ; 3A ; B[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
+; AB6 ; 43 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AB7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
; AB8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AB9 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB10 ; 61 ; 3B ; flags[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
+; AB10 ; 61 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AB11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AB12 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB13 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AB14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AB15 ; 105 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AB16 ; 111 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -505,15 +525,15 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; AC5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AC6 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AC7 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AC8 ; 62 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; 64 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC10 ; 59 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC8 ; 62 ; 3B ; B[3] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
+; AC9 ; 64 ; 3B ; B[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
+; AC10 ; 59 ; 3B ; op[1] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; AC11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AC12 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
; AC13 ; 102 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AC14 ; 104 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AC15 ; 103 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC16 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AC17 ; 127 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AC18 ; 120 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AC19 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -529,20 +549,20 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; AD3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AD4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AD5 ; 35 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AD6 ; 51 ; 3A ; op[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AD7 ; 53 ; 3A ; op[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
+; AD6 ; 51 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD7 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD8 ; 73 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD9 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AD10 ; 96 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD11 ; 88 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD12 ; 91 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; 93 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD13 ; 93 ; 4A ; B[2] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; AD14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AD15 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
; AD16 ; 119 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD17 ; 121 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD18 ; 118 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD19 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AD20 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD21 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD22 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -559,19 +579,19 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; AE7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AE8 ; 71 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE9 ; 77 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 94 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE10 ; 94 ; 4A ; B[1] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; AE11 ; 86 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AE12 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AE13 ; 109 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE14 ; 112 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE15 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AE18 ; 117 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 125 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE19 ; 125 ; 4A ; op[3] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; AE20 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE21 ; 131 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AE22 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AE23 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE24 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE25 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -589,7 +609,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; AF12 ; 99 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AF13 ; 107 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AF14 ; 110 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AF15 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AF16 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AF17 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AF18 ; 115 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -709,8 +729,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; F4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; F5 ; 398 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; F6 ; 360 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F7 ; 366 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F6 ; 360 ; 8A ; OUT_1[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
+; F7 ; 366 ; 8A ; OUT_1[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
; F8 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
; F9 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
@@ -735,8 +755,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; G3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
; G4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
; G5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G6 ; 362 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G7 ; 364 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G6 ; 362 ; 8A ; OUT_1[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
+; G7 ; 364 ; 8A ; OUT_1[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
; G8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; G9 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; G10 ; 357 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -762,7 +782,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; H4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; H5 ; 400 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
; H6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H7 ; 368 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H7 ; 368 ; 8A ; flags[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
; H8 ; 347 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; H9 ; 349 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; H10 ; 355 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -791,7 +811,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; J7 ; 370 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; J8 ; 365 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J10 ; 369 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J10 ; 369 ; 8A ; flags[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
; J11 ; 289 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; J12 ; 287 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; J13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
@@ -884,7 +904,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; M22 ; 224 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; M23 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; M24 ; 220 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 226 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M25 ; 226 ; 6A ; out_seg1[0] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
; M26 ; 228 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
@@ -919,11 +939,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; P6 ; 0 ; B1L ; GND ; ; ; ; Row I/O ; ; -- ; -- ;
; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P8 ; 52 ; 3A ; A[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
+; P8 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; P10 ; 74 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; P11 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; P12 ; 82 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; P11 ; 84 ; 3B ; A[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
+; P12 ; 82 ; 3B ; A[1] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; P13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; P14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
; P15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
@@ -945,9 +965,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; R5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ;
; R6 ; 30 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; R7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R8 ; 50 ; 3A ; B[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; R9 ; 48 ; 3A ; A[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; R10 ; 46 ; 3A ; B[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
+; R8 ; 50 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; R9 ; 48 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; R10 ; 46 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; R11 ; 60 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; R12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; R13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
@@ -972,7 +992,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; T6 ; 34 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
; T7 ; 38 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; T8 ; 40 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; T9 ; 56 ; 3B ; OUT_1[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
+; T9 ; 56 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; T11 ; 58 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; T12 ; 66 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -996,9 +1016,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; U5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ;
; U6 ; 31 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; U7 ; 39 ; 3A ; op[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; U8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U9 ; 54 ; 3B ; op[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
+; U7 ; 39 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; U8 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U9 ; 54 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; U10 ; 81 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; U11 ; 79 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; U12 ; 100 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -1007,7 +1027,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; U15 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; U16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; U17 ; 130 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; U18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; U18 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; U19 ; 167 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; U20 ; 181 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; U21 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
@@ -1025,16 +1045,16 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; V7 ; 28 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; V8 ; 41 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; V9 ; 70 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; V10 ; 72 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; V11 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V10 ; 72 ; 3B ; op[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
+; V11 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; V12 ; 98 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; V13 ; 92 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; V14 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; V15 ; 124 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; V18 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; V19 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V17 ; 154 ; 4A ; out_seg1[3] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
+; V18 ; 156 ; 4A ; out_seg1[2] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
+; V19 ; 164 ; 4A ; out_seg1[1] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; V20 ; 169 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; V21 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; V22 ; 175 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
@@ -1049,17 +1069,17 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; W5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; W6 ; 27 ; B0L ; GND ; ; ; ; Row I/O ; ; -- ; -- ;
; W7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W8 ; 42 ; 3A ; OUT_1[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
+; W8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; W10 ; 69 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; W11 ; 57 ; 3B ; B[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
+; W11 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W12 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; W14 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; W14 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; W15 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W17 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; W18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W18 ; 162 ; 4A ; out_seg1[4] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; W20 ; 171 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; W21 ; 173 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
@@ -1075,19 +1095,19 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; Y5 ; 32 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; Y6 ; 29 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;
; Y7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y8 ; 49 ; 3A ; A[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; Y9 ; 44 ; 3A ; OUT_1[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
+; Y8 ; 49 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y9 ; 44 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y10 ; 67 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y11 ; 55 ; 3B ; A[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
+; Y11 ; 55 ; 3B ; op[2] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; Y13 ; 95 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y14 ; 89 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 116 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y16 ; 114 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y18 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y15 ; 116 ; 4A ; A[2] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
+; Y16 ; 114 ; 4A ; A[3] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
+; Y17 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; Y18 ; 153 ; 4A ; out_seg1[7] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
+; Y19 ; 159 ; 4A ; out_seg1[6] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
+; Y20 ; 161 ; 4A ; out_seg1[5] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; Y21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; Y22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; Y23 ; 178 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
@@ -1098,48 +1118,27 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-+------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+-------------------------------+
-; Pin Name ; Reason ;
-+----------+-------------------------------+
-; OUT_1[0] ; Incomplete set of assignments ;
-; OUT_1[1] ; Incomplete set of assignments ;
-; OUT_1[2] ; Incomplete set of assignments ;
-; OUT_1[3] ; Incomplete set of assignments ;
-; flags[0] ; Incomplete set of assignments ;
-; flags[1] ; Incomplete set of assignments ;
-; op[2] ; Incomplete set of assignments ;
-; op[3] ; Incomplete set of assignments ;
-; B[0] ; Incomplete set of assignments ;
-; A[0] ; Incomplete set of assignments ;
-; op[0] ; Incomplete set of assignments ;
-; op[1] ; Incomplete set of assignments ;
-; B[3] ; Incomplete set of assignments ;
-; A[3] ; Incomplete set of assignments ;
-; B[1] ; Incomplete set of assignments ;
-; A[1] ; Incomplete set of assignments ;
-; B[2] ; Incomplete set of assignments ;
-; A[2] ; Incomplete set of assignments ;
-; OUT_1[0] ; Missing location assignment ;
-; OUT_1[1] ; Missing location assignment ;
-; OUT_1[2] ; Missing location assignment ;
-; OUT_1[3] ; Missing location assignment ;
-; flags[0] ; Missing location assignment ;
-; flags[1] ; Missing location assignment ;
-; op[2] ; Missing location assignment ;
-; op[3] ; Missing location assignment ;
-; B[0] ; Missing location assignment ;
-; A[0] ; Missing location assignment ;
-; op[0] ; Missing location assignment ;
-; op[1] ; Missing location assignment ;
-; B[3] ; Missing location assignment ;
-; A[3] ; Missing location assignment ;
-; B[1] ; Missing location assignment ;
-; A[1] ; Missing location assignment ;
-; B[2] ; Missing location assignment ;
-; A[2] ; Missing location assignment ;
-+----------+-------------------------------+
++----------------------------------------------------+
+; I/O Assignment Warnings ;
++-------------+--------------------------------------+
+; Pin Name ; Reason ;
++-------------+--------------------------------------+
+; OUT_1[0] ; Incomplete set of assignments ;
+; OUT_1[1] ; Incomplete set of assignments ;
+; OUT_1[2] ; Incomplete set of assignments ;
+; OUT_1[3] ; Incomplete set of assignments ;
+; flags[0] ; Missing drive strength and slew rate ;
+; flags[1] ; Incomplete set of assignments ;
+; out_seg1[0] ; Incomplete set of assignments ;
+; out_seg1[1] ; Missing drive strength and slew rate ;
+; out_seg1[2] ; Missing drive strength and slew rate ;
+; out_seg1[3] ; Missing drive strength and slew rate ;
+; out_seg1[4] ; Missing drive strength and slew rate ;
+; out_seg1[5] ; Missing drive strength and slew rate ;
+; out_seg1[6] ; Missing drive strength and slew rate ;
+; out_seg1[7] ; Missing drive strength and slew rate ;
+; out_seg1[0] ; Missing location assignment ;
++-------------+--------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -1147,36 +1146,45 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
-; |alu ; 10.5 (7.5) ; 10.5 (7.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 15 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 18 ; 0 ; |alu ; alu ; work ;
+; |alu ; 14.0 (7.5) ; 14.0 (7.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 26 ; 0 ; |alu ; alu ; work ;
; |asu:adder_unit| ; 3.0 (3.0) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |alu|asu:adder_unit ; asu ; work ;
+; |seven_seg:dut| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |alu|seven_seg:dut ; seven_seg ; work ;
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-+-------------------------------------------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; OUT_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; OUT_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; OUT_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; OUT_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; flags[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; flags[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; op[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; op[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; B[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; A[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; op[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; op[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; B[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; A[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; B[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; A[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; B[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; A[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
++----------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++-------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++-------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; OUT_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; OUT_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; OUT_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; OUT_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; flags[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; flags[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; out_seg1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; out_seg1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; out_seg1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; out_seg1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; out_seg1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; out_seg1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; out_seg1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; out_seg1[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; op[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; op[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; op[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; op[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; B[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; A[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; B[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; A[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; B[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; A[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; B[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; A[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
++-------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+----------------------------------------------------------------+
@@ -1185,13 +1193,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+----------------------------------+-------------------+---------+
; op[2] ; ; ;
-; - Mux0~0 ; 0 ; 0 ;
-; - Mux1~0 ; 0 ; 0 ;
-; - Mux2~0 ; 0 ; 0 ;
-; - Mux3~0 ; 0 ; 0 ;
-; - Mux3~1 ; 0 ; 0 ;
-; - Mux3~2 ; 0 ; 0 ;
-; - Mux3~3 ; 0 ; 0 ;
+; - Mux0~0 ; 1 ; 0 ;
+; - Mux1~0 ; 1 ; 0 ;
+; - Mux2~0 ; 1 ; 0 ;
+; - Mux3~0 ; 1 ; 0 ;
+; - Mux3~1 ; 1 ; 0 ;
+; - Mux3~2 ; 1 ; 0 ;
+; - Mux3~3 ; 1 ; 0 ;
; op[3] ; ; ;
; - Mux0~0 ; 1 ; 0 ;
; - Mux1~0 ; 1 ; 0 ;
@@ -1200,19 +1208,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; - Mux3~1 ; 1 ; 0 ;
; - Mux3~2 ; 1 ; 0 ;
; - Mux3~3 ; 1 ; 0 ;
-; B[0] ; ; ;
-; - asu:adder_unit|OUT_1[0] ; 1 ; 0 ;
-; - Mux3~1 ; 1 ; 0 ;
-; A[0] ; ; ;
-; - asu:adder_unit|OUT_1[0] ; 0 ; 0 ;
-; - Mux3~1 ; 0 ; 0 ;
; op[0] ; ; ;
-; - Mux0~0 ; 0 ; 0 ;
-; - Mux1~0 ; 0 ; 0 ;
-; - Mux2~0 ; 0 ; 0 ;
-; - Mux3~1 ; 0 ; 0 ;
-; - Mux3~2 ; 0 ; 0 ;
-; - Mux3~3 ; 0 ; 0 ;
+; - Mux0~0 ; 1 ; 0 ;
+; - Mux1~0 ; 1 ; 0 ;
+; - Mux2~0 ; 1 ; 0 ;
+; - Mux3~1 ; 1 ; 0 ;
+; - Mux3~2 ; 1 ; 0 ;
+; - Mux3~3 ; 1 ; 0 ;
; op[1] ; ; ;
; - Mux0~0 ; 1 ; 0 ;
; - Mux1~0 ; 1 ; 0 ;
@@ -1223,22 +1225,28 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; B[3] ; ; ;
; - asu:adder_unit|OUT_1[3] ; 1 ; 0 ;
; - Mux0~0 ; 1 ; 0 ;
-; - Mux3~3 ; 1 ; 0 ;
+; - Mux3~2 ; 1 ; 0 ;
; - asu:adder_unit|OUT_CIN[0] ; 1 ; 0 ;
; A[3] ; ; ;
-; - asu:adder_unit|OUT_1[3] ; 1 ; 0 ;
+; - asu:adder_unit|OUT_1[3] ; 0 ; 0 ;
+; - Mux3~2 ; 0 ; 0 ;
+; - asu:adder_unit|OUT_CIN[0] ; 0 ; 0 ;
+; - Mux0~0 ; 0 ; 0 ;
+; B[0] ; ; ;
+; - asu:adder_unit|OUT_1[0] ; 0 ; 0 ;
+; - Mux3~3 ; 0 ; 0 ;
+; A[0] ; ; ;
+; - asu:adder_unit|OUT_1[0] ; 1 ; 0 ;
; - Mux3~3 ; 1 ; 0 ;
-; - asu:adder_unit|OUT_CIN[0] ; 1 ; 0 ;
-; - Mux0~0 ; 1 ; 0 ;
; B[1] ; ; ;
; - asu:adder_unit|OUT_1[1] ; 0 ; 0 ;
; - Mux2~0 ; 0 ; 0 ;
; A[1] ; ; ;
-; - asu:adder_unit|OUT_1[1] ; 1 ; 0 ;
-; - Mux2~0 ; 1 ; 0 ;
+; - asu:adder_unit|OUT_1[1] ; 0 ; 0 ;
+; - Mux2~0 ; 0 ; 0 ;
; B[2] ; ; ;
-; - asu:adder_unit|OUT_1[2] ; 0 ; 0 ;
-; - Mux1~0 ; 0 ; 0 ;
+; - asu:adder_unit|OUT_1[2] ; 1 ; 0 ;
+; - Mux1~0 ; 1 ; 0 ;
; A[2] ; ; ;
; - asu:adder_unit|OUT_1[2] ; 1 ; 0 ;
; - Mux1~0 ; 1 ; 0 ;
@@ -1250,10 +1258,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------------------------------+------------------------+
; Routing Resource Type ; Usage ;
+------------------------------+------------------------+
-; Block interconnects ; 25 / 217,884 ( < 1 % ) ;
+; Block interconnects ; 37 / 217,884 ( < 1 % ) ;
; C12 interconnects ; 0 / 10,080 ( 0 % ) ;
-; C2 interconnects ; 12 / 87,208 ( < 1 % ) ;
-; C4 interconnects ; 7 / 41,360 ( < 1 % ) ;
+; C2 interconnects ; 22 / 87,208 ( < 1 % ) ;
+; C4 interconnects ; 96 / 41,360 ( < 1 % ) ;
; DQS bus muxes ; 0 / 21 ( 0 % ) ;
; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ;
; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ;
@@ -1262,10 +1270,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ;
; Local interconnects ; 6 / 58,160 ( < 1 % ) ;
; Quadrant clocks ; 0 / 88 ( 0 % ) ;
-; R14 interconnects ; 0 / 9,228 ( 0 % ) ;
-; R14/C12 interconnect drivers ; 0 / 15,096 ( 0 % ) ;
-; R3 interconnects ; 15 / 94,896 ( < 1 % ) ;
-; R6 interconnects ; 5 / 194,640 ( < 1 % ) ;
+; R14 interconnects ; 11 / 9,228 ( < 1 % ) ;
+; R14/C12 interconnect drivers ; 11 / 15,096 ( < 1 % ) ;
+; R3 interconnects ; 42 / 94,896 ( < 1 % ) ;
+; R6 interconnects ; 48 / 194,640 ( < 1 % ) ;
; Spine clocks ; 0 / 180 ( 0 % ) ;
; Wire stub REs ; 0 / 11,606 ( 0 % ) ;
+------------------------------+------------------------+
@@ -1277,10 +1285,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; I/O Rules Statistic ; Total ;
+----------------------------------+-------+
; Total I/O Rules ; 28 ;
-; Number of I/O Rules Passed ; 6 ;
+; Number of I/O Rules Passed ; 9 ;
; Number of I/O Rules Failed ; 0 ;
; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 22 ;
+; Number of I/O Rules Inapplicable ; 19 ;
+----------------------------------+-------+
@@ -1290,12 +1298,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
-; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
+; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ;
+; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
@@ -1326,28 +1334,36 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
-; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 18 ; 18 ; 0 ;
+; Total Pass ; 0 ; 25 ; 25 ; 0 ; 0 ; 26 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 26 ; 26 ; 0 ;
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 18 ; 18 ; 18 ; 18 ; 18 ; 0 ; 18 ; 18 ; 18 ; 18 ; 18 ; 18 ; 18 ; 12 ; 18 ; 18 ; 18 ; 18 ; 12 ; 18 ; 18 ; 18 ; 18 ; 12 ; 18 ; 0 ; 0 ; 18 ;
+; Total Inapplicable ; 26 ; 1 ; 1 ; 26 ; 26 ; 0 ; 1 ; 26 ; 26 ; 26 ; 26 ; 26 ; 26 ; 12 ; 26 ; 26 ; 26 ; 26 ; 12 ; 26 ; 26 ; 26 ; 26 ; 12 ; 26 ; 0 ; 0 ; 26 ;
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; OUT_1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; OUT_1[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; OUT_1[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; OUT_1[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; flags[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; flags[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; op[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; op[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; B[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; A[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; op[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; op[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; B[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; A[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; B[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; A[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; B[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; A[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; OUT_1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; OUT_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; OUT_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; OUT_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; flags[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; flags[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; out_seg1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; out_seg1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; out_seg1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; out_seg1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; out_seg1[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; out_seg1[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; out_seg1[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; out_seg1[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; op[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; op[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; op[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; op[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; B[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; A[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; B[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; A[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; B[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; A[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; B[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; A[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
@@ -1405,7 +1421,7 @@ Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (169085): No exact pin location assignment(s) for 18 pins of 18 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
+Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 26 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Info (184020): Starting Fitter periphery placement operations
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
Info (176233): Starting register packing
@@ -1421,27 +1437,28 @@ Info (332154): The derive_clock_uncertainty command did not apply clock uncertai
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
Info (170189): Fitter placement preparation operations beginning
Info (14951): The Fitter is using Advanced Physical Optimization.
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:02
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11
+ Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X33_Y11
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170200): Optimizations that may affect the design's timing were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
-Info (11888): Total time spent on timing analysis during the Fitter is 0.09 seconds.
+Info (11888): Total time spent on timing analysis during the Fitter is 0.08 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
-Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
-Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
- Info: Peak virtual memory: 1388 megabytes
- Info: Processing ended: Tue Sep 15 10:03:59 2026
- Info: Elapsed time: 00:00:30
- Info: Total CPU time (on all processors): 00:00:43
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info: Quartus Prime Fitter was successful. 0 errors, 7 warnings
+ Info: Peak virtual memory: 1341 megabytes
+ Info: Processing ended: Tue Sep 15 18:56:13 2026
+ Info: Elapsed time: 00:00:29
+ Info: Total CPU time (on all processors): 00:00:41
diff --git a/Quartus/A1_Q4/output_files/alu.fit.summary b/Quartus/A1_Q4/output_files/alu.fit.summary
index 5e80952..a09501d 100644
--- a/Quartus/A1_Q4/output_files/alu.fit.summary
+++ b/Quartus/A1_Q4/output_files/alu.fit.summary
@@ -1,13 +1,13 @@
-Fitter Status : Successful - Tue Sep 15 10:03:59 2026
+Fitter Status : Successful - Tue Sep 15 18:56:12 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : alu
Top-level Entity Name : alu
Family : Cyclone V
Device : 5CGXFC5C6F27C7
Timing Models : Final
-Logic utilization (in ALMs) : 11 / 29,080 ( < 1 % )
+Logic utilization (in ALMs) : 14 / 29,080 ( < 1 % )
Total registers : 0
-Total pins : 18 / 364 ( 5 % )
+Total pins : 26 / 364 ( 7 % )
Total virtual pins : 0
Total block memory bits : 0 / 4,567,040 ( 0 % )
Total RAM Blocks : 0 / 446 ( 0 % )
diff --git a/Quartus/A1_Q4/output_files/alu.flow.rpt b/Quartus/A1_Q4/output_files/alu.flow.rpt
index 2de001b..fff87c7 100644
--- a/Quartus/A1_Q4/output_files/alu.flow.rpt
+++ b/Quartus/A1_Q4/output_files/alu.flow.rpt
@@ -1,5 +1,5 @@
Flow report for alu
-Tue Sep 15 10:04:15 2026
+Tue Sep 15 18:56:29 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,16 +41,16 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
-; Flow Status ; Successful - Tue Sep 15 10:04:15 2026 ;
+; Flow Status ; Successful - Tue Sep 15 18:56:29 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; alu ;
; Top-level Entity Name ; alu ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
-; Logic utilization (in ALMs) ; 11 / 29,080 ( < 1 % ) ;
+; Logic utilization (in ALMs) ; 14 / 29,080 ( < 1 % ) ;
; Total registers ; 0 ;
-; Total pins ; 18 / 364 ( 5 % ) ;
+; Total pins ; 26 / 364 ( 7 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
; Total DSP Blocks ; 0 / 150 ( 0 % ) ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
-; Start date & time ; 09/15/2026 10:03:17 ;
+; Start date & time ; 09/15/2026 18:55:32 ;
; Main task ; Compilation ;
; Revision Name ; alu ;
+-------------------+---------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 253029099468756.178943059705529 ; -- ; -- ; -- ;
+; COMPILER_SIGNATURE_ID ; 268883478169649.178946253204767 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -101,12 +101,12 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:27 ;
-; Fitter ; 00:00:30 ; 1.0 ; 1388 MB ; 00:00:43 ;
-; Assembler ; 00:00:05 ; 1.0 ; 525 MB ; 00:00:05 ;
-; Timing Analyzer ; 00:00:06 ; 1.0 ; 793 MB ; 00:00:05 ;
-; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ;
-; Total ; 00:00:53 ; -- ; -- ; 00:01:21 ;
+; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 422 MB ; 00:00:25 ;
+; Fitter ; 00:00:28 ; 1.0 ; 1341 MB ; 00:00:40 ;
+; Assembler ; 00:00:06 ; 1.0 ; 514 MB ; 00:00:05 ;
+; Timing Analyzer ; 00:00:05 ; 1.0 ; 765 MB ; 00:00:05 ;
+; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 670 MB ; 00:00:01 ;
+; Total ; 00:00:51 ; -- ; -- ; 00:01:16 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
diff --git a/Quartus/A1_Q4/output_files/alu.map.rpt b/Quartus/A1_Q4/output_files/alu.map.rpt
index 8d1caf9..bbd8cab 100644
--- a/Quartus/A1_Q4/output_files/alu.map.rpt
+++ b/Quartus/A1_Q4/output_files/alu.map.rpt
@@ -1,5 +1,5 @@
Analysis & Synthesis report for alu
-Tue Sep 15 10:03:28 2026
+Tue Sep 15 18:55:43 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -18,9 +18,10 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
10. Parameter Settings for User Entity Instance: Top-level Entity: |alu
11. Parameter Settings for User Entity Instance: asu:adder_unit
12. Parameter Settings for User Entity Instance: lu:logic_unit
- 13. Post-Synthesis Netlist Statistics for Top Partition
- 14. Elapsed Time Per Partition
- 15. Analysis & Synthesis Messages
+ 13. Port Connectivity Checks: "seven_seg:dut"
+ 14. Post-Synthesis Netlist Statistics for Top Partition
+ 15. Elapsed Time Per Partition
+ 16. Analysis & Synthesis Messages
@@ -47,14 +48,14 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Tue Sep 15 10:03:28 2026 ;
+; Analysis & Synthesis Status ; Successful - Tue Sep 15 18:55:43 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; alu ;
; Top-level Entity Name ; alu ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A ;
; Total registers ; 0 ;
-; Total pins ; 18 ;
+; Total pins ; 26 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; Total DSP Blocks ; 0 ;
@@ -170,42 +171,43 @@ on the Quartus Prime software download page.
+----------------------------+-------------+
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+---------+
-; ../../modules/alu.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv ; ;
-; asu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/asu.sv ; ;
-; lu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/lu.sv ; ;
-+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+---------+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+
+; ../../modules/alu.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv ; ;
+; asu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/asu.sv ; ;
+; lu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/lu.sv ; ;
+; seven_seg.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/seven_seg.sv ; ;
++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+
-+-----------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+-------------+
-; Resource ; Usage ;
-+---------------------------------------------+-------------+
-; Estimate of Logic utilization (ALMs needed) ; 10 ;
-; ; ;
-; Combinational ALUT usage for logic ; 14 ;
-; -- 7 input functions ; 3 ;
-; -- 6 input functions ; 3 ;
-; -- 5 input functions ; 0 ;
-; -- 4 input functions ; 1 ;
-; -- <=3 input functions ; 7 ;
-; ; ;
-; Dedicated logic registers ; 0 ;
-; ; ;
-; I/O pins ; 18 ;
-; ; ;
-; Total DSP Blocks ; 0 ;
-; ; ;
-; Maximum fan-out node ; op[2]~input ;
-; Maximum fan-out ; 7 ;
-; Total fan-out ; 84 ;
-; Average fan-out ; 1.68 ;
-+---------------------------------------------+-------------+
++------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+--------+
+; Resource ; Usage ;
++---------------------------------------------+--------+
+; Estimate of Logic utilization (ALMs needed) ; 14 ;
+; ; ;
+; Combinational ALUT usage for logic ; 21 ;
+; -- 7 input functions ; 3 ;
+; -- 6 input functions ; 3 ;
+; -- 5 input functions ; 0 ;
+; -- 4 input functions ; 8 ;
+; -- <=3 input functions ; 7 ;
+; ; ;
+; Dedicated logic registers ; 0 ;
+; ; ;
+; I/O pins ; 26 ;
+; ; ;
+; Total DSP Blocks ; 0 ;
+; ; ;
+; Maximum fan-out node ; Mux0~0 ;
+; Maximum fan-out ; 8 ;
+; Total fan-out ; 127 ;
+; Average fan-out ; 1.74 ;
++---------------------------------------------+--------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -213,8 +215,9 @@ on the Quartus Prime software download page.
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
-; |alu ; 14 (8) ; 0 (0) ; 0 ; 0 ; 18 ; 0 ; |alu ; alu ; work ;
+; |alu ; 21 (8) ; 0 (0) ; 0 ; 0 ; 26 ; 0 ; |alu ; alu ; work ;
; |asu:adder_unit| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |alu|asu:adder_unit ; asu ; work ;
+; |seven_seg:dut| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |alu|seven_seg:dut ; seven_seg ; work ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -273,26 +276,38 @@ Note: In order to hide this table in the UI and the text report file, please set
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "seven_seg:dut" ;
++------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; rbi_inv ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; rbi_inv[0] ; Input ; Info ; Stuck at VCC ;
++------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
-; arriav_lcell_comb ; 14 ;
+; arriav_lcell_comb ; 23 ;
; extend ; 3 ;
; 7 data inputs ; 3 ;
-; normal ; 6 ;
+; normal ; 15 ;
+; 0 data inputs ; 1 ;
+; 1 data inputs ; 1 ;
; 2 data inputs ; 1 ;
; 3 data inputs ; 1 ;
-; 4 data inputs ; 1 ;
+; 4 data inputs ; 8 ;
; 6 data inputs ; 3 ;
; shared ; 5 ;
; 0 data inputs ; 1 ;
; 2 data inputs ; 4 ;
-; boundary_port ; 18 ;
+; boundary_port ; 26 ;
; ; ;
-; Max LUT depth ; 2.40 ;
-; Average LUT depth ; 2.20 ;
+; Max LUT depth ; 4.40 ;
+; Average LUT depth ; 3.96 ;
+-----------------------+-----------------------------+
@@ -311,28 +326,33 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
- Info: Processing started: Tue Sep 15 10:03:17 2026
+ Info: Processing started: Tue Sep 15 18:55:32 2026
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
-Info (12021): Found 3 design units, including 3 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv
+Info (12021): Found 4 design units, including 4 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv
Info (12023): Found entity 1: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/asu.sv Line: 4
Info (12023): Found entity 2: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/lu.sv Line: 3
- Info (12023): Found entity 3: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 9
+ Info (12023): Found entity 3: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/seven_seg.sv Line: 3
+ Info (12023): Found entity 4: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 10
Info (12127): Elaborating entity "alu" for the top level hierarchy
-Info (12128): Elaborating entity "asu" for hierarchy "asu:adder_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 16
-Info (12128): Elaborating entity "lu" for hierarchy "lu:logic_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 19
+Info (12128): Elaborating entity "asu" for hierarchy "asu:adder_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 18
+Info (12128): Elaborating entity "lu" for hierarchy "lu:logic_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 21
+Info (12128): Elaborating entity "seven_seg" for hierarchy "seven_seg:dut" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 38
+Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13024): Output pins are stuck at VCC or GND
+ Warning (13410): Pin "out_seg1[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 13
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 32 device resources after synthesis - the final resource count might be different
+Info (21057): Implemented 47 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 12 input pins
- Info (21059): Implemented 6 output pins
- Info (21061): Implemented 14 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 436 megabytes
- Info: Processing ended: Tue Sep 15 10:03:28 2026
+ Info (21059): Implemented 14 output pins
+ Info (21061): Implemented 21 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings
+ Info: Peak virtual memory: 439 megabytes
+ Info: Processing ended: Tue Sep 15 18:55:43 2026
Info: Elapsed time: 00:00:11
- Info: Total CPU time (on all processors): 00:00:27
+ Info: Total CPU time (on all processors): 00:00:25
diff --git a/Quartus/A1_Q4/output_files/alu.map.summary b/Quartus/A1_Q4/output_files/alu.map.summary
index 99da5d5..fc068ea 100644
--- a/Quartus/A1_Q4/output_files/alu.map.summary
+++ b/Quartus/A1_Q4/output_files/alu.map.summary
@@ -1,11 +1,11 @@
-Analysis & Synthesis Status : Successful - Tue Sep 15 10:03:28 2026
+Analysis & Synthesis Status : Successful - Tue Sep 15 18:55:43 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : alu
Top-level Entity Name : alu
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 0
-Total pins : 18
+Total pins : 26
Total virtual pins : 0
Total block memory bits : 0
Total DSP Blocks : 0
diff --git a/Quartus/A1_Q4/output_files/alu.pin b/Quartus/A1_Q4/output_files/alu.pin
index c6fd3cf..2493605 100644
--- a/Quartus/A1_Q4/output_files/alu.pin
+++ b/Quartus/A1_Q4/output_files/alu.pin
@@ -29,8 +29,8 @@
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 3A: 2.5V
- -- Bank 3B: 2.5V
- -- Bank 4A: 2.5V
+ -- Bank 3B: 1.2V
+ -- Bank 4A: 1.2V
-- Bank 5A: 2.5V
-- Bank 5B: 2.5V
-- Bank 6A: 2.5V
@@ -105,11 +105,11 @@ GND : AA2 : gnd : :
GXB_NC : AA3 : : : : B0L :
GXB_NC : AA4 : : : : B0L :
GND : AA5 : gnd : : : :
-OUT_1[0] : AA6 : output : 2.5 V : : 3A : N
-flags[1] : AA7 : output : 2.5 V : : 3A : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3A :
VCC_AUX : AA8 : power : : 2.5V : :
VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : :
-VCCIO3B : AA10 : power : : 2.5V : 3B :
+VCCIO3B : AA10 : power : : 1.2V : 3B :
VCCPD3B4A : AA11 : power : : 2.5V : 3B, 4A :
NC : AA12 : : : : :
VCCPD3B4A : AA13 : power : : 2.5V : 3B, 4A :
@@ -119,7 +119,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : :
VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A :
-VCCIO4A : AA20 : power : : 2.5V : 4A :
+VCCIO4A : AA20 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A :
@@ -131,14 +131,14 @@ GND : AB2 : : :
GND : AB3 : gnd : : : :
GND : AB4 : gnd : : : :
AS_DATA2, DATA2 : AB5 : : : : 3A :
-B[1] : AB6 : input : 2.5 V : : 3A : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3A :
NC : AB7 : : : : :
GND : AB8 : gnd : : : :
VCCPD3A : AB9 : power : : 2.5V : 3A :
-flags[0] : AB10 : output : 2.5 V : : 3B : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B :
-VCCIO4A : AB13 : power : : 2.5V : 4A :
+VCCIO4A : AB13 : power : : 1.2V : 4A :
VCC_AUX : AB14 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A :
@@ -159,15 +159,15 @@ GXB_NC : AC4 : : :
GND : AC5 : gnd : : : :
VCCIO3A : AC6 : power : : 2.5V : 3A :
VREFB3AN0 : AC7 : power : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3B :
+B[3] : AC8 : input : 1.2 V : : 3B : Y
+B[0] : AC9 : input : 1.2 V : : 3B : Y
+op[1] : AC10 : input : 1.2 V : : 3B : Y
GND : AC11 : gnd : : : :
VREFB3BN0 : AC12 : power : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4A :
-VCCIO4A : AC16 : power : : 2.5V : 4A :
+VCCIO4A : AC16 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4A :
@@ -183,20 +183,20 @@ GND : AD2 : : :
GND : AD3 : gnd : : : :
GND : AD4 : gnd : : : :
AS_DATA1, DATA1 : AD5 : : : : 3A :
-op[0] : AD6 : input : 2.5 V : : 3A : N
-op[2] : AD7 : input : 2.5 V : : 3A : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B :
-VCCIO3B : AD9 : power : : 2.5V : 3B :
+VCCIO3B : AD9 : power : : 1.2V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD13 : : : : 4A :
+B[2] : AD13 : input : 1.2 V : : 4A : Y
GND : AD14 : gnd : : : :
VREFB4AN0 : AD15 : power : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4A :
-VCCIO4A : AD19 : power : : 2.5V : 4A :
+VCCIO4A : AD19 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4A :
@@ -213,19 +213,19 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : :
GND : AE7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 4A :
+B[1] : AE10 : input : 1.2 V : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 4A :
-VCCIO4A : AE12 : power : : 2.5V : 4A :
+VCCIO4A : AE12 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
GND : AE17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
+op[3] : AE19 : input : 1.2 V : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4A :
-VCCIO4A : AE22 : power : : 2.5V : 4A :
+VCCIO4A : AE22 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4A :
@@ -243,7 +243,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A :
-VCCIO4A : AF15 : power : : 2.5V : 4A :
+VCCIO4A : AF15 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
@@ -363,8 +363,8 @@ NC : F2 : : :
GND : F3 : gnd : : : :
GND : F4 : gnd : : : :
nCONFIG : F5 : : : : 9A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8A :
+OUT_1[1] : F6 : output : 2.5 V : : 8A : Y
+OUT_1[0] : F7 : output : 2.5 V : : 8A : Y
VCCPGM : F8 : power : : 1.8V/2.5V/3.0V/3.3V : :
VCCPD7A8A : F9 : power : : 2.5V : 7A, 8A :
GND : F10 : gnd : : : :
@@ -389,8 +389,8 @@ GND : G2 : gnd : :
NC : G3 : : : : :
NC : G4 : : : : :
GND : G5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
+OUT_1[2] : G6 : output : 2.5 V : : 8A : Y
+OUT_1[3] : G7 : output : 2.5 V : : 8A : Y
VCCIO8A : G8 : power : : 2.5V : 8A :
VCC_AUX : G9 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
@@ -416,7 +416,7 @@ GND : H3 : gnd : :
GND : H4 : gnd : : : :
GND : H5 : : : : 9A :
GND : H6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A :
+flags[0] : H7 : output : 2.5 V : : 8A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H9 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8A :
@@ -445,7 +445,7 @@ VCCA_FPLL : J6 : power : : 2.5V
RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 8A :
GND : J9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A :
+flags[1] : J10 : output : 2.5 V : : 8A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7A :
VCC : J13 : power : : 1.1V : :
@@ -538,7 +538,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
VCCIO6A : M23 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
+out_seg1[0] : M25 : output : 2.5 V : : 6A : N
RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
GND : N1 : gnd : : : :
GND : N2 : gnd : : : :
@@ -573,11 +573,11 @@ VCCE_GXBL : P4 : power : : 1.1V
GND : P5 : gnd : : : :
GND : P6 : : : : B1L :
GND : P7 : gnd : : : :
-A[0] : P8 : input : 2.5 V : : 3A : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3A :
GND : P9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 3B :
+A[0] : P11 : input : 1.2 V : : 3B : Y
+A[1] : P12 : input : 1.2 V : : 3B : Y
GND : P13 : gnd : : : :
VCC : P14 : power : : 1.1V : :
GND : P15 : gnd : : : :
@@ -599,9 +599,9 @@ GND : R4 : gnd : :
VCCE_GXBL : R5 : power : : 1.1V : :
TMS : R6 : input : : : 3A :
GND : R7 : gnd : : : :
-B[2] : R8 : input : 2.5 V : : 3A : N
-A[2] : R9 : input : 2.5 V : : 3A : N
-B[3] : R10 : input : 2.5 V : : 3A : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3B :
GND : R12 : gnd : : : :
VCC : R13 : power : : 1.1V : :
@@ -626,7 +626,7 @@ GND : T5 : gnd : :
TDI : T6 : input : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3A :
-OUT_1[2] : T9 : output : 2.5 V : : 3B : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 3B :
GND : T10 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 3B :
@@ -650,9 +650,9 @@ VCCL_GXBL : U3 : power : : 1.1V
GND : U4 : gnd : : : :
VCCE_GXBL : U5 : power : : 1.1V : :
AS_DATA3, DATA3 : U6 : : : : 3A :
-op[1] : U7 : input : 2.5 V : : 3A : N
-VCCIO3B : U8 : power : : 2.5V : 3B :
-op[3] : U9 : input : 2.5 V : : 3B : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A :
+VCCIO3B : U8 : power : : 1.2V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U12 : : : : 4A :
@@ -661,7 +661,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4A :
-VCCIO4A : U18 : power : : 2.5V : 4A :
+VCCIO4A : U18 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A :
VCCPD5A : U21 : power : : 2.5V : 5A :
@@ -679,16 +679,16 @@ GND : V6 : : :
TDO : V7 : output : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3B :
-VCCIO3B : V11 : power : : 2.5V : 3B :
+op[0] : V10 : input : 1.2 V : : 3B : Y
+VCCIO3B : V11 : power : : 1.2V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4A :
GND : V16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V19 : : : : 4A :
+out_seg1[3] : V17 : output : 1.2 V : : 4A : Y
+out_seg1[2] : V18 : output : 1.2 V : : 4A : Y
+out_seg1[1] : V19 : output : 1.2 V : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5A :
VCCIO5A : V21 : power : : 2.5V : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5A :
@@ -703,17 +703,17 @@ GXB_NC : W4 : : :
GND : W5 : gnd : : : :
GND : W6 : : : : B0L :
VCCA_FPLL : W7 : power : : 2.5V : :
-OUT_1[3] : W8 : output : 2.5 V : : 3A : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A :
GND : W9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3B :
-B[0] : W11 : input : 2.5 V : : 3B : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A :
-VCCIO4A : W14 : power : : 2.5V : 4A :
+VCCIO4A : W14 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4A :
+out_seg1[4] : W18 : output : 1.2 V : : 4A : Y
GND : W19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A :
@@ -729,19 +729,19 @@ GND : Y4 : gnd : :
TCK : Y5 : input : : : 3A :
nCSO, DATA4 : Y6 : : : : 3A :
VCCIO3A : Y7 : power : : 2.5V : 3A :
-A[3] : Y8 : input : 2.5 V : : 3A : N
-OUT_1[1] : Y9 : output : 2.5 V : : 3A : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y9 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3B :
-A[1] : Y11 : input : 2.5 V : : 3B : N
+op[2] : Y11 : input : 1.2 V : : 3B : Y
GND : Y12 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A :
-VCCIO4A : Y17 : power : : 2.5V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 4A :
+A[2] : Y15 : input : 1.2 V : : 4A : Y
+A[3] : Y16 : input : 1.2 V : : 4A : Y
+VCCIO4A : Y17 : power : : 1.2V : 4A :
+out_seg1[7] : Y18 : output : 1.2 V : : 4A : Y
+out_seg1[6] : Y19 : output : 1.2 V : : 4A : Y
+out_seg1[5] : Y20 : output : 1.2 V : : 4A : Y
VCCA_FPLL : Y21 : power : : 2.5V : :
GND : Y22 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A :
diff --git a/Quartus/A1_Q4/output_files/alu.sof b/Quartus/A1_Q4/output_files/alu.sof
index 466d322..e3fa432 100644
Binary files a/Quartus/A1_Q4/output_files/alu.sof and b/Quartus/A1_Q4/output_files/alu.sof differ
diff --git a/Quartus/A1_Q4/output_files/alu.sta.rpt b/Quartus/A1_Q4/output_files/alu.sta.rpt
index 6647ebd..ba80d5d 100644
--- a/Quartus/A1_Q4/output_files/alu.sta.rpt
+++ b/Quartus/A1_Q4/output_files/alu.sta.rpt
@@ -1,5 +1,5 @@
Timing Analyzer report for alu
-Tue Sep 15 10:04:13 2026
+Tue Sep 15 18:56:26 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -98,12 +98,12 @@ on the Quartus Prime software download page.
; Number detected on machine ; 4 ;
; Maximum allowed ; 2 ;
; ; ;
-; Average used ; 1.02 ;
+; Average used ; 1.03 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
-; Processor 2 ; 2.1% ;
+; Processor 2 ; 3.4% ;
+----------------------------+-------------+
@@ -285,18 +285,26 @@ No synchronizer chains to report.
+------------------+-------+------+----------+---------+---------------------+
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; OUT_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; OUT_1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; OUT_1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; OUT_1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; flags[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; flags[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments ;
++-------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++-------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; OUT_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; OUT_1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; OUT_1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; OUT_1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; flags[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; flags[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; out_seg1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; out_seg1[1] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; out_seg1[2] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; out_seg1[3] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; out_seg1[4] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; out_seg1[5] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; out_seg1[6] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; out_seg1[7] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
++-------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+----------------------------------------------------------+
@@ -304,75 +312,107 @@ No synchronizer chains to report.
+-------+--------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------+--------------+-----------------+-----------------+
-; op[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; op[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; B[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; A[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; op[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; op[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; B[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; A[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; B[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; A[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; B[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; A[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
+; op[2] ; 1.2 V ; 960 ps ; 960 ps ;
+; op[3] ; 1.2 V ; 960 ps ; 960 ps ;
+; op[0] ; 1.2 V ; 960 ps ; 960 ps ;
+; op[1] ; 1.2 V ; 960 ps ; 960 ps ;
+; B[3] ; 1.2 V ; 960 ps ; 960 ps ;
+; A[3] ; 1.2 V ; 960 ps ; 960 ps ;
+; B[0] ; 1.2 V ; 960 ps ; 960 ps ;
+; A[0] ; 1.2 V ; 960 ps ; 960 ps ;
+; B[1] ; 1.2 V ; 960 ps ; 960 ps ;
+; A[1] ; 1.2 V ; 960 ps ; 960 ps ;
+; B[2] ; 1.2 V ; 960 ps ; 960 ps ;
+; A[2] ; 1.2 V ; 960 ps ; 960 ps ;
+-------+--------------+-----------------+-----------------+
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
-+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
-; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
-; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
-; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
-; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
-; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
-+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
++-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
+; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
+; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
+; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
+; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
+; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
+; out_seg1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
+; out_seg1[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
+; out_seg1[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
+; out_seg1[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ;
+; out_seg1[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ;
+; out_seg1[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
+; out_seg1[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ;
+; out_seg1[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
++-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
-+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
-; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
-; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
-; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
-; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
-; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
-+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
++-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
+; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
+; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
+; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
+; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
+; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
+; out_seg1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
+; out_seg1[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
+; out_seg1[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
+; out_seg1[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ;
+; out_seg1[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ;
+; out_seg1[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
+; out_seg1[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ;
+; out_seg1[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
++-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
-+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
-; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
++-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
+; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
+; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
+; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
+; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
+; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
+; out_seg1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
+; out_seg1[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
+; out_seg1[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
+; out_seg1[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ;
+; out_seg1[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ;
+; out_seg1[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
+; out_seg1[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ;
+; out_seg1[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
++-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
-+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
-; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
++-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
+; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
+; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
+; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
+; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
+; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
+; out_seg1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
+; out_seg1[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
+; out_seg1[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
+; out_seg1[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ;
+; out_seg1[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ;
+; out_seg1[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
+; out_seg1[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ;
+; out_seg1[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
++-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-------------------
@@ -401,9 +441,9 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 12 ; 12 ;
-; Unconstrained Input Port Paths ; 58 ; 58 ;
-; Unconstrained Output Ports ; 6 ; 6 ;
-; Unconstrained Output Port Paths ; 58 ; 58 ;
+; Unconstrained Input Port Paths ; 142 ; 142 ;
+; Unconstrained Output Ports ; 13 ; 13 ;
+; Unconstrained Output Port Paths ; 142 ; 142 ;
+---------------------------------+-------+------+
@@ -438,6 +478,13 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; flags[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; flags[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out_seg1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out_seg1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out_seg1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out_seg1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out_seg1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out_seg1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out_seg1[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
@@ -472,6 +519,13 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; flags[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; flags[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out_seg1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out_seg1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out_seg1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out_seg1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out_seg1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out_seg1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out_seg1[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
@@ -481,7 +535,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
- Info: Processing started: Tue Sep 15 10:04:07 2026
+ Info: Processing started: Tue Sep 15 18:56:21 2026
Info: Command: quartus_sta A1_Q4 -c alu
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@@ -541,9 +595,9 @@ Info (332140): No Minimum Pulse Width paths to report
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
- Info: Peak virtual memory: 793 megabytes
- Info: Processing ended: Tue Sep 15 10:04:13 2026
- Info: Elapsed time: 00:00:06
+ Info: Peak virtual memory: 765 megabytes
+ Info: Processing ended: Tue Sep 15 18:56:26 2026
+ Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05
diff --git a/Quartus/A1_Q4/seven_seg.sv b/Quartus/A1_Q4/seven_seg.sv
new file mode 100644
index 0000000..675f354
--- /dev/null
+++ b/Quartus/A1_Q4/seven_seg.sv
@@ -0,0 +1,26 @@
+`ifndef SEVEN_SEG_H_SV
+`define SEVEN_SEG_H_SV
+module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments);
+ always_comb begin
+ case (num)
+ 4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000);
+ 4'b0001: segments = ~(8'b00001101);
+ 4'b0010: segments = ~(8'b10110111);
+ 4'b0011: segments = ~(8'b10011111);
+ 4'b0100: segments = ~(8'b11001101);
+ 4'b0101: segments = ~(8'b11011011);
+ 4'b0110: segments = ~(8'b11111011);
+ 4'b0111: segments = ~(8'b00001111);
+ 4'b1000: segments = ~(8'b11111111);
+ 4'b1001: segments = ~(8'b11001111);
+ 4'b1010: segments = ~(8'b11101111);
+ 4'b1011: segments = ~(8'b11111001);
+ 4'b1100: segments = ~(8'b01110011);
+ 4'b1101: segments = ~(8'b10111101);
+ 4'b1110: segments = ~(8'b11110011);
+ 4'b1111: segments = ~(8'b11100011);
+ default: segments = ~(8'bxxxxxxxx);
+ endcase
+ end
+endmodule
+`endif
\ No newline at end of file
diff --git a/Quartus/A1_Q4/simulation/questa/alu.svo b/Quartus/A1_Q4/simulation/questa/alu.svo
index a1a9cb5..52c16b9 100644
--- a/Quartus/A1_Q4/simulation/questa/alu.svo
+++ b/Quartus/A1_Q4/simulation/questa/alu.svo
@@ -17,7 +17,7 @@
// PROGRAM "Quartus Prime"
// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
-// DATE "09/15/2026 10:04:15"
+// DATE "09/15/2026 18:56:29"
//
// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
@@ -34,32 +34,42 @@ module alu (
A,
B,
OUT_1,
- flags);
-input logic [3:0] op ;
-input logic [3:0] A ;
-input logic [3:0] B ;
-output logic [3:0] OUT_1 ;
-output logic [1:0] flags ;
+ flags,
+ out_seg1);
+input [3:0] op;
+input [3:0] A;
+input [3:0] B;
+output [3:0] OUT_1;
+output [1:0] flags;
+output [7:0] out_seg1;
// Design Ports Information
-// OUT_1[0] => Location: PIN_AA6, I/O Standard: 2.5 V, Current Strength: Default
-// OUT_1[1] => Location: PIN_Y9, I/O Standard: 2.5 V, Current Strength: Default
-// OUT_1[2] => Location: PIN_T9, I/O Standard: 2.5 V, Current Strength: Default
-// OUT_1[3] => Location: PIN_W8, I/O Standard: 2.5 V, Current Strength: Default
-// flags[0] => Location: PIN_AB10, I/O Standard: 2.5 V, Current Strength: Default
-// flags[1] => Location: PIN_AA7, I/O Standard: 2.5 V, Current Strength: Default
-// op[2] => Location: PIN_AD7, I/O Standard: 2.5 V, Current Strength: Default
-// op[3] => Location: PIN_U9, I/O Standard: 2.5 V, Current Strength: Default
-// B[0] => Location: PIN_W11, I/O Standard: 2.5 V, Current Strength: Default
-// A[0] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default
-// op[0] => Location: PIN_AD6, I/O Standard: 2.5 V, Current Strength: Default
-// op[1] => Location: PIN_U7, I/O Standard: 2.5 V, Current Strength: Default
-// B[3] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default
-// A[3] => Location: PIN_Y8, I/O Standard: 2.5 V, Current Strength: Default
-// B[1] => Location: PIN_AB6, I/O Standard: 2.5 V, Current Strength: Default
-// A[1] => Location: PIN_Y11, I/O Standard: 2.5 V, Current Strength: Default
-// B[2] => Location: PIN_R8, I/O Standard: 2.5 V, Current Strength: Default
-// A[2] => Location: PIN_R9, I/O Standard: 2.5 V, Current Strength: Default
+// OUT_1[0] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default
+// OUT_1[1] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default
+// OUT_1[2] => Location: PIN_G6, I/O Standard: 2.5 V, Current Strength: Default
+// OUT_1[3] => Location: PIN_G7, I/O Standard: 2.5 V, Current Strength: Default
+// flags[0] => Location: PIN_H7, I/O Standard: 2.5 V, Current Strength: Default
+// flags[1] => Location: PIN_J10, I/O Standard: 2.5 V, Current Strength: Default
+// out_seg1[0] => Location: PIN_M25, I/O Standard: 2.5 V, Current Strength: Default
+// out_seg1[1] => Location: PIN_V19, I/O Standard: 1.2 V, Current Strength: Default
+// out_seg1[2] => Location: PIN_V18, I/O Standard: 1.2 V, Current Strength: Default
+// out_seg1[3] => Location: PIN_V17, I/O Standard: 1.2 V, Current Strength: Default
+// out_seg1[4] => Location: PIN_W18, I/O Standard: 1.2 V, Current Strength: Default
+// out_seg1[5] => Location: PIN_Y20, I/O Standard: 1.2 V, Current Strength: Default
+// out_seg1[6] => Location: PIN_Y19, I/O Standard: 1.2 V, Current Strength: Default
+// out_seg1[7] => Location: PIN_Y18, I/O Standard: 1.2 V, Current Strength: Default
+// op[2] => Location: PIN_Y11, I/O Standard: 1.2 V, Current Strength: Default
+// op[3] => Location: PIN_AE19, I/O Standard: 1.2 V, Current Strength: Default
+// op[0] => Location: PIN_V10, I/O Standard: 1.2 V, Current Strength: Default
+// op[1] => Location: PIN_AC10, I/O Standard: 1.2 V, Current Strength: Default
+// B[3] => Location: PIN_AC8, I/O Standard: 1.2 V, Current Strength: Default
+// A[3] => Location: PIN_Y16, I/O Standard: 1.2 V, Current Strength: Default
+// B[0] => Location: PIN_AC9, I/O Standard: 1.2 V, Current Strength: Default
+// A[0] => Location: PIN_P11, I/O Standard: 1.2 V, Current Strength: Default
+// B[1] => Location: PIN_AE10, I/O Standard: 1.2 V, Current Strength: Default
+// A[1] => Location: PIN_P12, I/O Standard: 1.2 V, Current Strength: Default
+// B[2] => Location: PIN_AD13, I/O Standard: 1.2 V, Current Strength: Default
+// A[2] => Location: PIN_Y15, I/O Standard: 1.2 V, Current Strength: Default
wire gnd;
@@ -74,16 +84,18 @@ tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \~QUARTUS_CREATED_GND~I_combout ;
+wire \op[3]~input_o ;
+wire \op[1]~input_o ;
wire \op[0]~input_o ;
+wire \op[2]~input_o ;
+wire \Mux3~1_combout ;
+wire \Mux3~0_combout ;
+wire \B[0]~input_o ;
+wire \A[0]~input_o ;
+wire \Mux3~3_combout ;
wire \B[3]~input_o ;
wire \A[3]~input_o ;
-wire \op[2]~input_o ;
-wire \op[1]~input_o ;
-wire \op[3]~input_o ;
-wire \Mux3~3_combout ;
-wire \A[0]~input_o ;
-wire \B[0]~input_o ;
-wire \Mux3~0_combout ;
+wire \Mux3~2_combout ;
wire \B[2]~input_o ;
wire \A[2]~input_o ;
wire \A[1]~input_o ;
@@ -96,18 +108,23 @@ wire \adder_unit|_~10 ;
wire \adder_unit|_~11 ;
wire \adder_unit|_~13 ;
wire \adder_unit|_~14 ;
-wire \Mux3~2_combout ;
-wire \Mux3~1_combout ;
wire \Mux3~4_combout ;
wire \Mux2~0_combout ;
wire \Mux1~0_combout ;
wire \Mux0~0_combout ;
+wire \dut|Mux5~0_combout ;
+wire \dut|Mux4~0_combout ;
+wire \dut|Mux3~0_combout ;
+wire \dut|Mux2~0_combout ;
+wire \dut|Mux1~0_combout ;
+wire \dut|Mux0~0_combout ;
+wire \dut|WideOr0~0_combout ;
wire [0:0] \adder_unit|OUT_CIN ;
wire [3:0] \adder_unit|OUT_1 ;
wire [0:0] \adder_unit|COUT ;
-// Location: IOOBUF_X4_Y0_N36
+// Location: IOOBUF_X14_Y61_N53
cyclonev_io_obuf \OUT_1[0]~output (
.i(\Mux3~4_combout ),
.oe(vcc),
@@ -123,7 +140,7 @@ defparam \OUT_1[0]~output .open_drain_output = "false";
defparam \OUT_1[0]~output .shift_series_termination_control = "false";
// synopsys translate_on
-// Location: IOOBUF_X4_Y0_N2
+// Location: IOOBUF_X15_Y61_N36
cyclonev_io_obuf \OUT_1[1]~output (
.i(\Mux2~0_combout ),
.oe(vcc),
@@ -139,7 +156,7 @@ defparam \OUT_1[1]~output .open_drain_output = "false";
defparam \OUT_1[1]~output .shift_series_termination_control = "false";
// synopsys translate_on
-// Location: IOOBUF_X10_Y0_N76
+// Location: IOOBUF_X15_Y61_N53
cyclonev_io_obuf \OUT_1[2]~output (
.i(\Mux1~0_combout ),
.oe(vcc),
@@ -155,7 +172,7 @@ defparam \OUT_1[2]~output .open_drain_output = "false";
defparam \OUT_1[2]~output .shift_series_termination_control = "false";
// synopsys translate_on
-// Location: IOOBUF_X4_Y0_N19
+// Location: IOOBUF_X14_Y61_N36
cyclonev_io_obuf \OUT_1[3]~output (
.i(\Mux0~0_combout ),
.oe(vcc),
@@ -171,7 +188,7 @@ defparam \OUT_1[3]~output .open_drain_output = "false";
defparam \OUT_1[3]~output .shift_series_termination_control = "false";
// synopsys translate_on
-// Location: IOOBUF_X12_Y0_N36
+// Location: IOOBUF_X12_Y61_N36
cyclonev_io_obuf \flags[0]~output (
.i(\adder_unit|COUT [0]),
.oe(vcc),
@@ -187,7 +204,7 @@ defparam \flags[0]~output .open_drain_output = "false";
defparam \flags[0]~output .shift_series_termination_control = "false";
// synopsys translate_on
-// Location: IOOBUF_X6_Y0_N53
+// Location: IOOBUF_X12_Y61_N19
cyclonev_io_obuf \flags[1]~output (
.i(\adder_unit|OUT_CIN [0]),
.oe(vcc),
@@ -203,62 +220,135 @@ defparam \flags[1]~output .open_drain_output = "false";
defparam \flags[1]~output .shift_series_termination_control = "false";
// synopsys translate_on
-// Location: IOIBUF_X7_Y0_N52
-cyclonev_io_ibuf \op[0]~input (
- .i(op[0]),
- .ibar(gnd),
+// Location: IOOBUF_X68_Y37_N5
+cyclonev_io_obuf \out_seg1[0]~output (
+ .i(gnd),
+ .oe(vcc),
.dynamicterminationcontrol(gnd),
- .o(\op[0]~input_o ));
+ .seriesterminationcontrol(16'b0000000000000000),
+ .parallelterminationcontrol(16'b0000000000000000),
+ .devoe(devoe),
+ .o(out_seg1[0]),
+ .obar());
// synopsys translate_off
-defparam \op[0]~input .bus_hold = "false";
-defparam \op[0]~input .simulate_z_as = "z";
+defparam \out_seg1[0]~output .bus_hold = "false";
+defparam \out_seg1[0]~output .open_drain_output = "false";
+defparam \out_seg1[0]~output .shift_series_termination_control = "false";
// synopsys translate_on
-// Location: IOIBUF_X6_Y0_N18
-cyclonev_io_ibuf \B[3]~input (
- .i(B[3]),
- .ibar(gnd),
+// Location: IOOBUF_X66_Y0_N2
+cyclonev_io_obuf \out_seg1[1]~output (
+ .i(\dut|Mux5~0_combout ),
+ .oe(vcc),
.dynamicterminationcontrol(gnd),
- .o(\B[3]~input_o ));
+ .seriesterminationcontrol(16'b0000000000000000),
+ .parallelterminationcontrol(16'b0000000000000000),
+ .devoe(devoe),
+ .o(out_seg1[1]),
+ .obar());
// synopsys translate_off
-defparam \B[3]~input .bus_hold = "false";
-defparam \B[3]~input .simulate_z_as = "z";
+defparam \out_seg1[1]~output .bus_hold = "false";
+defparam \out_seg1[1]~output .open_drain_output = "false";
+defparam \out_seg1[1]~output .shift_series_termination_control = "false";
// synopsys translate_on
-// Location: IOIBUF_X6_Y0_N35
-cyclonev_io_ibuf \A[3]~input (
- .i(A[3]),
- .ibar(gnd),
+// Location: IOOBUF_X64_Y0_N2
+cyclonev_io_obuf \out_seg1[2]~output (
+ .i(\dut|Mux4~0_combout ),
+ .oe(vcc),
.dynamicterminationcontrol(gnd),
- .o(\A[3]~input_o ));
+ .seriesterminationcontrol(16'b0000000000000000),
+ .parallelterminationcontrol(16'b0000000000000000),
+ .devoe(devoe),
+ .o(out_seg1[2]),
+ .obar());
// synopsys translate_off
-defparam \A[3]~input .bus_hold = "false";
-defparam \A[3]~input .simulate_z_as = "z";
+defparam \out_seg1[2]~output .bus_hold = "false";
+defparam \out_seg1[2]~output .open_drain_output = "false";
+defparam \out_seg1[2]~output .shift_series_termination_control = "false";
// synopsys translate_on
-// Location: IOIBUF_X7_Y0_N35
-cyclonev_io_ibuf \op[2]~input (
- .i(op[2]),
- .ibar(gnd),
+// Location: IOOBUF_X64_Y0_N19
+cyclonev_io_obuf \out_seg1[3]~output (
+ .i(\dut|Mux3~0_combout ),
+ .oe(vcc),
.dynamicterminationcontrol(gnd),
- .o(\op[2]~input_o ));
+ .seriesterminationcontrol(16'b0000000000000000),
+ .parallelterminationcontrol(16'b0000000000000000),
+ .devoe(devoe),
+ .o(out_seg1[3]),
+ .obar());
// synopsys translate_off
-defparam \op[2]~input .bus_hold = "false";
-defparam \op[2]~input .simulate_z_as = "z";
+defparam \out_seg1[3]~output .bus_hold = "false";
+defparam \out_seg1[3]~output .open_drain_output = "false";
+defparam \out_seg1[3]~output .shift_series_termination_control = "false";
// synopsys translate_on
-// Location: IOIBUF_X2_Y0_N92
-cyclonev_io_ibuf \op[1]~input (
- .i(op[1]),
- .ibar(gnd),
+// Location: IOOBUF_X66_Y0_N19
+cyclonev_io_obuf \out_seg1[4]~output (
+ .i(\dut|Mux2~0_combout ),
+ .oe(vcc),
.dynamicterminationcontrol(gnd),
- .o(\op[1]~input_o ));
+ .seriesterminationcontrol(16'b0000000000000000),
+ .parallelterminationcontrol(16'b0000000000000000),
+ .devoe(devoe),
+ .o(out_seg1[4]),
+ .obar());
// synopsys translate_off
-defparam \op[1]~input .bus_hold = "false";
-defparam \op[1]~input .simulate_z_as = "z";
+defparam \out_seg1[4]~output .bus_hold = "false";
+defparam \out_seg1[4]~output .open_drain_output = "false";
+defparam \out_seg1[4]~output .shift_series_termination_control = "false";
// synopsys translate_on
-// Location: IOIBUF_X10_Y0_N92
+// Location: IOOBUF_X65_Y0_N2
+cyclonev_io_obuf \out_seg1[5]~output (
+ .i(\dut|Mux1~0_combout ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(16'b0000000000000000),
+ .parallelterminationcontrol(16'b0000000000000000),
+ .devoe(devoe),
+ .o(out_seg1[5]),
+ .obar());
+// synopsys translate_off
+defparam \out_seg1[5]~output .bus_hold = "false";
+defparam \out_seg1[5]~output .open_drain_output = "false";
+defparam \out_seg1[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X65_Y0_N19
+cyclonev_io_obuf \out_seg1[6]~output (
+ .i(\dut|Mux0~0_combout ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(16'b0000000000000000),
+ .parallelterminationcontrol(16'b0000000000000000),
+ .devoe(devoe),
+ .o(out_seg1[6]),
+ .obar());
+// synopsys translate_off
+defparam \out_seg1[6]~output .bus_hold = "false";
+defparam \out_seg1[6]~output .open_drain_output = "false";
+defparam \out_seg1[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X62_Y0_N42
+cyclonev_io_obuf \out_seg1[7]~output (
+ .i(!\dut|WideOr0~0_combout ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(16'b0000000000000000),
+ .parallelterminationcontrol(16'b0000000000000000),
+ .devoe(devoe),
+ .o(out_seg1[7]),
+ .obar());
+// synopsys translate_off
+defparam \out_seg1[7]~output .bus_hold = "false";
+defparam \out_seg1[7]~output .open_drain_output = "false";
+defparam \out_seg1[7]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X50_Y0_N35
cyclonev_io_ibuf \op[3]~input (
.i(op[3]),
.ibar(gnd),
@@ -269,42 +359,88 @@ defparam \op[3]~input .bus_hold = "false";
defparam \op[3]~input .simulate_z_as = "z";
// synopsys translate_on
-// Location: LABCELL_X7_Y1_N18
-cyclonev_lcell_comb \Mux3~3 (
-// Equation(s):
-// \Mux3~3_combout = ( \op[1]~input_o & ( \op[3]~input_o & ( (!\op[0]~input_o & (!\op[2]~input_o & (!\B[3]~input_o $ (!\A[3]~input_o )))) ) ) )
+// Location: IOIBUF_X12_Y0_N52
+cyclonev_io_ibuf \op[1]~input (
+ .i(op[1]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\op[1]~input_o ));
+// synopsys translate_off
+defparam \op[1]~input .bus_hold = "false";
+defparam \op[1]~input .simulate_z_as = "z";
+// synopsys translate_on
- .dataa(!\op[0]~input_o ),
- .datab(!\B[3]~input_o ),
- .datac(!\A[3]~input_o ),
- .datad(!\op[2]~input_o ),
- .datae(!\op[1]~input_o ),
- .dataf(!\op[3]~input_o ),
+// Location: IOIBUF_X17_Y0_N75
+cyclonev_io_ibuf \op[0]~input (
+ .i(op[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\op[0]~input_o ));
+// synopsys translate_off
+defparam \op[0]~input .bus_hold = "false";
+defparam \op[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X10_Y0_N58
+cyclonev_io_ibuf \op[2]~input (
+ .i(op[2]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\op[2]~input_o ));
+// synopsys translate_off
+defparam \op[2]~input .bus_hold = "false";
+defparam \op[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X23_Y1_N18
+cyclonev_lcell_comb \Mux3~1 (
+// Equation(s):
+// \Mux3~1_combout = ( !\op[2]~input_o & ( (\op[3]~input_o & (\op[1]~input_o & \op[0]~input_o )) ) )
+
+ .dataa(gnd),
+ .datab(!\op[3]~input_o ),
+ .datac(!\op[1]~input_o ),
+ .datad(!\op[0]~input_o ),
+ .datae(gnd),
+ .dataf(!\op[2]~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
- .combout(\Mux3~3_combout ),
+ .combout(\Mux3~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
-defparam \Mux3~3 .extended_lut = "off";
-defparam \Mux3~3 .lut_mask = 64'h0000000000002800;
-defparam \Mux3~3 .shared_arith = "off";
+defparam \Mux3~1 .extended_lut = "off";
+defparam \Mux3~1 .lut_mask = 64'h0003000300000000;
+defparam \Mux3~1 .shared_arith = "off";
// synopsys translate_on
-// Location: IOIBUF_X7_Y0_N1
-cyclonev_io_ibuf \A[0]~input (
- .i(A[0]),
- .ibar(gnd),
- .dynamicterminationcontrol(gnd),
- .o(\A[0]~input_o ));
+// Location: LABCELL_X22_Y1_N3
+cyclonev_lcell_comb \Mux3~0 (
+// Equation(s):
+// \Mux3~0_combout = ( !\op[3]~input_o & ( !\op[2]~input_o ) )
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(!\op[2]~input_o ),
+ .datad(gnd),
+ .datae(!\op[3]~input_o ),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\Mux3~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
// synopsys translate_off
-defparam \A[0]~input .bus_hold = "false";
-defparam \A[0]~input .simulate_z_as = "z";
+defparam \Mux3~0 .extended_lut = "off";
+defparam \Mux3~0 .lut_mask = 64'hF0F00000F0F00000;
+defparam \Mux3~0 .shared_arith = "off";
// synopsys translate_on
-// Location: IOIBUF_X10_Y0_N41
+// Location: IOIBUF_X14_Y0_N35
cyclonev_io_ibuf \B[0]~input (
.i(B[0]),
.ibar(gnd),
@@ -315,16 +451,52 @@ defparam \B[0]~input .bus_hold = "false";
defparam \B[0]~input .simulate_z_as = "z";
// synopsys translate_on
-// Location: LABCELL_X7_Y1_N30
+// Location: IOIBUF_X21_Y0_N1
+cyclonev_io_ibuf \A[0]~input (
+ .i(A[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\A[0]~input_o ));
+// synopsys translate_off
+defparam \A[0]~input .bus_hold = "false";
+defparam \A[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X23_Y1_N48
+cyclonev_lcell_comb \Mux3~3 (
+// Equation(s):
+// \Mux3~3_combout = ( !\op[3]~input_o & ( \A[0]~input_o & ( (\op[2]~input_o & (!\op[1]~input_o $ (((!\op[0]~input_o & !\B[0]~input_o ))))) ) ) ) # ( !\op[3]~input_o & ( !\A[0]~input_o & ( (\op[2]~input_o & ((!\op[0]~input_o & (\op[1]~input_o &
+// \B[0]~input_o )) # (\op[0]~input_o & (!\op[1]~input_o $ (!\B[0]~input_o ))))) ) ) )
+
+ .dataa(!\op[0]~input_o ),
+ .datab(!\op[2]~input_o ),
+ .datac(!\op[1]~input_o ),
+ .datad(!\B[0]~input_o ),
+ .datae(!\op[3]~input_o ),
+ .dataf(!\A[0]~input_o ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\Mux3~3_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \Mux3~3 .extended_lut = "off";
+defparam \Mux3~3 .lut_mask = 64'h0112000012300000;
+defparam \Mux3~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X23_Y1_N30
cyclonev_lcell_comb \adder_unit|OUT_1[0] (
// Equation(s):
-// \adder_unit|OUT_1 [0] = SUM(( !\A[0]~input_o $ (!\B[0]~input_o ) ) + ( !VCC ) + ( !VCC ))
-// \adder_unit|_~1 = CARRY(( !\A[0]~input_o $ (!\B[0]~input_o ) ) + ( !VCC ) + ( !VCC ))
-// \adder_unit|_~2 = SHARE((\A[0]~input_o & \B[0]~input_o ))
+// \adder_unit|OUT_1 [0] = SUM(( !\B[0]~input_o $ (!\A[0]~input_o ) ) + ( !VCC ) + ( !VCC ))
+// \adder_unit|_~1 = CARRY(( !\B[0]~input_o $ (!\A[0]~input_o ) ) + ( !VCC ) + ( !VCC ))
+// \adder_unit|_~2 = SHARE((\B[0]~input_o & \A[0]~input_o ))
.dataa(gnd),
- .datab(!\A[0]~input_o ),
- .datac(!\B[0]~input_o ),
+ .datab(!\B[0]~input_o ),
+ .datac(!\A[0]~input_o ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
@@ -341,31 +513,54 @@ defparam \adder_unit|OUT_1[0] .lut_mask = 64'h0000030300003C3C;
defparam \adder_unit|OUT_1[0] .shared_arith = "on";
// synopsys translate_on
-// Location: LABCELL_X7_Y1_N51
-cyclonev_lcell_comb \Mux3~0 (
-// Equation(s):
-// \Mux3~0_combout = (!\op[3]~input_o & !\op[2]~input_o )
+// Location: IOIBUF_X14_Y0_N52
+cyclonev_io_ibuf \B[3]~input (
+ .i(B[3]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\B[3]~input_o ));
+// synopsys translate_off
+defparam \B[3]~input .bus_hold = "false";
+defparam \B[3]~input .simulate_z_as = "z";
+// synopsys translate_on
- .dataa(!\op[3]~input_o ),
+// Location: IOIBUF_X46_Y0_N18
+cyclonev_io_ibuf \A[3]~input (
+ .i(A[3]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\A[3]~input_o ));
+// synopsys translate_off
+defparam \A[3]~input .bus_hold = "false";
+defparam \A[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X23_Y1_N54
+cyclonev_lcell_comb \Mux3~2 (
+// Equation(s):
+// \Mux3~2_combout = ( \op[3]~input_o & ( \A[3]~input_o & ( (!\B[3]~input_o & (!\op[2]~input_o & (\op[1]~input_o & !\op[0]~input_o ))) ) ) ) # ( \op[3]~input_o & ( !\A[3]~input_o & ( (\B[3]~input_o & (!\op[2]~input_o & (\op[1]~input_o &
+// !\op[0]~input_o ))) ) ) )
+
+ .dataa(!\B[3]~input_o ),
.datab(!\op[2]~input_o ),
- .datac(gnd),
- .datad(gnd),
- .datae(gnd),
- .dataf(gnd),
+ .datac(!\op[1]~input_o ),
+ .datad(!\op[0]~input_o ),
+ .datae(!\op[3]~input_o ),
+ .dataf(!\A[3]~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
- .combout(\Mux3~0_combout ),
+ .combout(\Mux3~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
-defparam \Mux3~0 .extended_lut = "off";
-defparam \Mux3~0 .lut_mask = 64'h8888888888888888;
-defparam \Mux3~0 .shared_arith = "off";
+defparam \Mux3~2 .extended_lut = "off";
+defparam \Mux3~2 .lut_mask = 64'h0000040000000800;
+defparam \Mux3~2 .shared_arith = "off";
// synopsys translate_on
-// Location: IOIBUF_X7_Y0_N18
+// Location: IOIBUF_X34_Y0_N35
cyclonev_io_ibuf \B[2]~input (
.i(B[2]),
.ibar(gnd),
@@ -376,7 +571,7 @@ defparam \B[2]~input .bus_hold = "false";
defparam \B[2]~input .simulate_z_as = "z";
// synopsys translate_on
-// Location: IOIBUF_X6_Y0_N1
+// Location: IOIBUF_X46_Y0_N1
cyclonev_io_ibuf \A[2]~input (
.i(A[2]),
.ibar(gnd),
@@ -387,7 +582,7 @@ defparam \A[2]~input .bus_hold = "false";
defparam \A[2]~input .simulate_z_as = "z";
// synopsys translate_on
-// Location: IOIBUF_X10_Y0_N58
+// Location: IOIBUF_X21_Y0_N18
cyclonev_io_ibuf \A[1]~input (
.i(A[1]),
.ibar(gnd),
@@ -398,7 +593,7 @@ defparam \A[1]~input .bus_hold = "false";
defparam \A[1]~input .simulate_z_as = "z";
// synopsys translate_on
-// Location: IOIBUF_X4_Y0_N52
+// Location: IOIBUF_X36_Y0_N52
cyclonev_io_ibuf \B[1]~input (
.i(B[1]),
.ibar(gnd),
@@ -409,7 +604,7 @@ defparam \B[1]~input .bus_hold = "false";
defparam \B[1]~input .simulate_z_as = "z";
// synopsys translate_on
-// Location: LABCELL_X7_Y1_N33
+// Location: LABCELL_X23_Y1_N33
cyclonev_lcell_comb \adder_unit|OUT_1[1] (
// Equation(s):
// \adder_unit|OUT_1 [1] = SUM(( !\A[1]~input_o $ (!\B[1]~input_o ) ) + ( \adder_unit|_~2 ) + ( \adder_unit|_~1 ))
@@ -418,8 +613,8 @@ cyclonev_lcell_comb \adder_unit|OUT_1[1] (
.dataa(!\A[1]~input_o ),
.datab(gnd),
- .datac(!\B[1]~input_o ),
- .datad(gnd),
+ .datac(gnd),
+ .datad(!\B[1]~input_o ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
@@ -431,11 +626,11 @@ cyclonev_lcell_comb \adder_unit|OUT_1[1] (
.shareout(\adder_unit|_~8 ));
// synopsys translate_off
defparam \adder_unit|OUT_1[1] .extended_lut = "off";
-defparam \adder_unit|OUT_1[1] .lut_mask = 64'h0000050500005A5A;
+defparam \adder_unit|OUT_1[1] .lut_mask = 64'h00000055000055AA;
defparam \adder_unit|OUT_1[1] .shared_arith = "on";
// synopsys translate_on
-// Location: LABCELL_X7_Y1_N36
+// Location: LABCELL_X23_Y1_N36
cyclonev_lcell_comb \adder_unit|OUT_1[2] (
// Equation(s):
// \adder_unit|OUT_1 [2] = SUM(( !\B[2]~input_o $ (!\A[2]~input_o ) ) + ( \adder_unit|_~8 ) + ( \adder_unit|_~7 ))
@@ -443,9 +638,9 @@ cyclonev_lcell_comb \adder_unit|OUT_1[2] (
// \adder_unit|_~11 = SHARE((\B[2]~input_o & \A[2]~input_o ))
.dataa(gnd),
- .datab(gnd),
- .datac(!\B[2]~input_o ),
- .datad(!\A[2]~input_o ),
+ .datab(!\B[2]~input_o ),
+ .datac(!\A[2]~input_o ),
+ .datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
@@ -457,20 +652,20 @@ cyclonev_lcell_comb \adder_unit|OUT_1[2] (
.shareout(\adder_unit|_~11 ));
// synopsys translate_off
defparam \adder_unit|OUT_1[2] .extended_lut = "off";
-defparam \adder_unit|OUT_1[2] .lut_mask = 64'h0000000F00000FF0;
+defparam \adder_unit|OUT_1[2] .lut_mask = 64'h0000030300003C3C;
defparam \adder_unit|OUT_1[2] .shared_arith = "on";
// synopsys translate_on
-// Location: LABCELL_X7_Y1_N39
+// Location: LABCELL_X23_Y1_N39
cyclonev_lcell_comb \adder_unit|OUT_1[3] (
// Equation(s):
-// \adder_unit|OUT_1 [3] = SUM(( !\A[3]~input_o $ (!\B[3]~input_o ) ) + ( \adder_unit|_~11 ) + ( \adder_unit|_~10 ))
-// \adder_unit|_~13 = CARRY(( !\A[3]~input_o $ (!\B[3]~input_o ) ) + ( \adder_unit|_~11 ) + ( \adder_unit|_~10 ))
-// \adder_unit|_~14 = SHARE((\A[3]~input_o & \B[3]~input_o ))
+// \adder_unit|OUT_1 [3] = SUM(( !\B[3]~input_o $ (!\A[3]~input_o ) ) + ( \adder_unit|_~11 ) + ( \adder_unit|_~10 ))
+// \adder_unit|_~13 = CARRY(( !\B[3]~input_o $ (!\A[3]~input_o ) ) + ( \adder_unit|_~11 ) + ( \adder_unit|_~10 ))
+// \adder_unit|_~14 = SHARE((\B[3]~input_o & \A[3]~input_o ))
- .dataa(!\A[3]~input_o ),
+ .dataa(!\B[3]~input_o ),
.datab(gnd),
- .datac(!\B[3]~input_o ),
+ .datac(!\A[3]~input_o ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
@@ -487,7 +682,7 @@ defparam \adder_unit|OUT_1[3] .lut_mask = 64'h0000050500005A5A;
defparam \adder_unit|OUT_1[3] .shared_arith = "on";
// synopsys translate_on
-// Location: LABCELL_X7_Y1_N42
+// Location: LABCELL_X23_Y1_N42
cyclonev_lcell_comb \adder_unit|COUT[0] (
// Equation(s):
// \adder_unit|COUT [0] = SUM(( GND ) + ( \adder_unit|_~14 ) + ( \adder_unit|_~13 ))
@@ -511,67 +706,18 @@ defparam \adder_unit|COUT[0] .lut_mask = 64'h0000000000000000;
defparam \adder_unit|COUT[0] .shared_arith = "on";
// synopsys translate_on
-// Location: LABCELL_X7_Y1_N48
-cyclonev_lcell_comb \Mux3~2 (
-// Equation(s):
-// \Mux3~2_combout = (\op[3]~input_o & (!\op[2]~input_o & (\op[0]~input_o & \op[1]~input_o )))
-
- .dataa(!\op[3]~input_o ),
- .datab(!\op[2]~input_o ),
- .datac(!\op[0]~input_o ),
- .datad(!\op[1]~input_o ),
- .datae(gnd),
- .dataf(gnd),
- .datag(gnd),
- .cin(gnd),
- .sharein(gnd),
- .combout(\Mux3~2_combout ),
- .sumout(),
- .cout(),
- .shareout());
-// synopsys translate_off
-defparam \Mux3~2 .extended_lut = "off";
-defparam \Mux3~2 .lut_mask = 64'h0004000400040004;
-defparam \Mux3~2 .shared_arith = "off";
-// synopsys translate_on
-
-// Location: LABCELL_X7_Y1_N24
-cyclonev_lcell_comb \Mux3~1 (
-// Equation(s):
-// \Mux3~1_combout = ( \op[2]~input_o & ( !\op[3]~input_o & ( (!\B[0]~input_o & ((!\op[1]~input_o & (\op[0]~input_o & \A[0]~input_o )) # (\op[1]~input_o & (!\op[0]~input_o $ (!\A[0]~input_o ))))) # (\B[0]~input_o & (!\op[1]~input_o $
-// (((!\op[0]~input_o & !\A[0]~input_o ))))) ) ) )
-
- .dataa(!\B[0]~input_o ),
- .datab(!\op[1]~input_o ),
- .datac(!\op[0]~input_o ),
- .datad(!\A[0]~input_o ),
- .datae(!\op[2]~input_o ),
- .dataf(!\op[3]~input_o ),
- .datag(gnd),
- .cin(gnd),
- .sharein(gnd),
- .combout(\Mux3~1_combout ),
- .sumout(),
- .cout(),
- .shareout());
-// synopsys translate_off
-defparam \Mux3~1 .extended_lut = "off";
-defparam \Mux3~1 .lut_mask = 64'h0000166C00000000;
-defparam \Mux3~1 .shared_arith = "off";
-// synopsys translate_on
-
-// Location: LABCELL_X7_Y1_N54
+// Location: LABCELL_X23_Y1_N24
cyclonev_lcell_comb \Mux3~4 (
// Equation(s):
-// \Mux3~4_combout = ( \Mux3~2_combout & ( \Mux3~1_combout ) ) # ( !\Mux3~2_combout & ( \Mux3~1_combout ) ) # ( \Mux3~2_combout & ( !\Mux3~1_combout & ( ((!\adder_unit|COUT [0]) # ((\adder_unit|OUT_1 [0] & \Mux3~0_combout ))) # (\Mux3~3_combout ) ) )
-// ) # ( !\Mux3~2_combout & ( !\Mux3~1_combout & ( ((\adder_unit|OUT_1 [0] & \Mux3~0_combout )) # (\Mux3~3_combout ) ) ) )
+// \Mux3~4_combout = ( \Mux3~2_combout & ( \adder_unit|COUT [0] ) ) # ( !\Mux3~2_combout & ( \adder_unit|COUT [0] & ( ((\Mux3~0_combout & \adder_unit|OUT_1 [0])) # (\Mux3~3_combout ) ) ) ) # ( \Mux3~2_combout & ( !\adder_unit|COUT [0] ) ) # (
+// !\Mux3~2_combout & ( !\adder_unit|COUT [0] & ( (((\Mux3~0_combout & \adder_unit|OUT_1 [0])) # (\Mux3~3_combout )) # (\Mux3~1_combout ) ) ) )
- .dataa(!\Mux3~3_combout ),
- .datab(!\adder_unit|OUT_1 [0]),
- .datac(!\Mux3~0_combout ),
- .datad(!\adder_unit|COUT [0]),
+ .dataa(!\Mux3~1_combout ),
+ .datab(!\Mux3~0_combout ),
+ .datac(!\Mux3~3_combout ),
+ .datad(!\adder_unit|OUT_1 [0]),
.datae(!\Mux3~2_combout ),
- .dataf(!\Mux3~1_combout ),
+ .dataf(!\adder_unit|COUT [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
@@ -581,22 +727,22 @@ cyclonev_lcell_comb \Mux3~4 (
.shareout());
// synopsys translate_off
defparam \Mux3~4 .extended_lut = "off";
-defparam \Mux3~4 .lut_mask = 64'h5757FF57FFFFFFFF;
+defparam \Mux3~4 .lut_mask = 64'h5F7FFFFF0F3FFFFF;
defparam \Mux3~4 .shared_arith = "off";
// synopsys translate_on
-// Location: LABCELL_X7_Y1_N12
+// Location: LABCELL_X23_Y1_N12
cyclonev_lcell_comb \Mux2~0 (
// Equation(s):
-// \Mux2~0_combout = ( !\op[2]~input_o & ( (((\adder_unit|OUT_1 [1] & ((!\op[3]~input_o ))))) ) ) # ( \op[2]~input_o & ( (!\op[3]~input_o & ((!\op[0]~input_o & ((!\op[1]~input_o & (\A[1]~input_o & \B[1]~input_o )) # (\op[1]~input_o & (!\A[1]~input_o
-// $ (!\B[1]~input_o ))))) # (\op[0]~input_o & (!\op[1]~input_o $ (((!\A[1]~input_o & !\B[1]~input_o ))))))) ) )
+// \Mux2~0_combout = ( !\op[2]~input_o & ( (((\adder_unit|OUT_1 [1] & (!\op[3]~input_o )))) ) ) # ( \op[2]~input_o & ( (!\op[3]~input_o & ((!\B[1]~input_o & ((!\op[0]~input_o & (\A[1]~input_o & \op[1]~input_o )) # (\op[0]~input_o & (!\A[1]~input_o $
+// (!\op[1]~input_o ))))) # (\B[1]~input_o & (!\op[1]~input_o $ (((!\op[0]~input_o & !\A[1]~input_o ))))))) ) )
- .dataa(!\op[0]~input_o ),
- .datab(!\op[1]~input_o ),
+ .dataa(!\B[1]~input_o ),
+ .datab(!\op[0]~input_o ),
.datac(!\A[1]~input_o ),
- .datad(!\B[1]~input_o ),
+ .datad(!\op[3]~input_o ),
.datae(!\op[2]~input_o ),
- .dataf(!\op[3]~input_o ),
+ .dataf(!\op[1]~input_o ),
.datag(!\adder_unit|OUT_1 [1]),
.cin(gnd),
.sharein(gnd),
@@ -606,22 +752,22 @@ cyclonev_lcell_comb \Mux2~0 (
.shareout());
// synopsys translate_off
defparam \Mux2~0 .extended_lut = "on";
-defparam \Mux2~0 .lut_mask = 64'h0F0F166C00000000;
+defparam \Mux2~0 .lut_mask = 64'h0F0017000F006800;
defparam \Mux2~0 .shared_arith = "off";
// synopsys translate_on
-// Location: LABCELL_X7_Y1_N6
+// Location: LABCELL_X23_Y1_N6
cyclonev_lcell_comb \Mux1~0 (
// Equation(s):
-// \Mux1~0_combout = ( !\op[2]~input_o & ( (((\adder_unit|OUT_1 [2] & ((!\op[3]~input_o ))))) ) ) # ( \op[2]~input_o & ( (!\op[3]~input_o & ((!\op[0]~input_o & ((!\op[1]~input_o & (\A[2]~input_o & \B[2]~input_o )) # (\op[1]~input_o & (!\A[2]~input_o
-// $ (!\B[2]~input_o ))))) # (\op[0]~input_o & (!\op[1]~input_o $ (((!\A[2]~input_o & !\B[2]~input_o ))))))) ) )
+// \Mux1~0_combout = ( !\op[2]~input_o & ( ((!\op[3]~input_o & (\adder_unit|OUT_1 [2]))) ) ) # ( \op[2]~input_o & ( (!\op[3]~input_o & ((!\A[2]~input_o & ((!\op[1]~input_o & (\B[2]~input_o & \op[0]~input_o )) # (\op[1]~input_o & (!\B[2]~input_o $
+// (!\op[0]~input_o ))))) # (\A[2]~input_o & (!\op[1]~input_o $ (((!\B[2]~input_o & !\op[0]~input_o ))))))) ) )
- .dataa(!\op[0]~input_o ),
- .datab(!\op[1]~input_o ),
+ .dataa(!\op[1]~input_o ),
+ .datab(!\op[3]~input_o ),
.datac(!\A[2]~input_o ),
.datad(!\B[2]~input_o ),
.datae(!\op[2]~input_o ),
- .dataf(!\op[3]~input_o ),
+ .dataf(!\op[0]~input_o ),
.datag(!\adder_unit|OUT_1 [2]),
.cin(gnd),
.sharein(gnd),
@@ -631,22 +777,22 @@ cyclonev_lcell_comb \Mux1~0 (
.shareout());
// synopsys translate_off
defparam \Mux1~0 .extended_lut = "on";
-defparam \Mux1~0 .lut_mask = 64'h0F0F166C00000000;
+defparam \Mux1~0 .lut_mask = 64'h0C0C04480C0C4888;
defparam \Mux1~0 .shared_arith = "off";
// synopsys translate_on
-// Location: LABCELL_X7_Y1_N0
+// Location: LABCELL_X23_Y1_N0
cyclonev_lcell_comb \Mux0~0 (
// Equation(s):
-// \Mux0~0_combout = ( !\op[2]~input_o & ( (((\adder_unit|OUT_1 [3] & ((!\op[3]~input_o ))))) ) ) # ( \op[2]~input_o & ( (!\op[3]~input_o & ((!\op[0]~input_o & ((!\op[1]~input_o & (\A[3]~input_o & \B[3]~input_o )) # (\op[1]~input_o & (!\A[3]~input_o
-// $ (!\B[3]~input_o ))))) # (\op[0]~input_o & (!\op[1]~input_o $ (((!\A[3]~input_o & !\B[3]~input_o ))))))) ) )
+// \Mux0~0_combout = ( !\op[2]~input_o & ( (((\adder_unit|OUT_1 [3] & (!\op[3]~input_o )))) ) ) # ( \op[2]~input_o & ( (!\op[3]~input_o & ((!\B[3]~input_o & ((!\op[0]~input_o & (\A[3]~input_o & \op[1]~input_o )) # (\op[0]~input_o & (!\A[3]~input_o $
+// (!\op[1]~input_o ))))) # (\B[3]~input_o & (!\op[1]~input_o $ (((!\op[0]~input_o & !\A[3]~input_o ))))))) ) )
- .dataa(!\op[0]~input_o ),
- .datab(!\op[1]~input_o ),
+ .dataa(!\B[3]~input_o ),
+ .datab(!\op[0]~input_o ),
.datac(!\A[3]~input_o ),
- .datad(!\B[3]~input_o ),
+ .datad(!\op[3]~input_o ),
.datae(!\op[2]~input_o ),
- .dataf(!\op[3]~input_o ),
+ .dataf(!\op[1]~input_o ),
.datag(!\adder_unit|OUT_1 [3]),
.cin(gnd),
.sharein(gnd),
@@ -656,22 +802,21 @@ cyclonev_lcell_comb \Mux0~0 (
.shareout());
// synopsys translate_off
defparam \Mux0~0 .extended_lut = "on";
-defparam \Mux0~0 .lut_mask = 64'h0F0F166C00000000;
+defparam \Mux0~0 .lut_mask = 64'h0F0017000F006800;
defparam \Mux0~0 .shared_arith = "off";
// synopsys translate_on
-// Location: MLABCELL_X6_Y1_N0
+// Location: LABCELL_X23_Y1_N21
cyclonev_lcell_comb \adder_unit|OUT_CIN[0] (
// Equation(s):
-// \adder_unit|OUT_CIN [0] = ( \A[3]~input_o & ( \adder_unit|OUT_1 [3] & ( \B[3]~input_o ) ) ) # ( !\A[3]~input_o & ( \adder_unit|OUT_1 [3] & ( !\B[3]~input_o ) ) ) # ( \A[3]~input_o & ( !\adder_unit|OUT_1 [3] & ( !\B[3]~input_o ) ) ) # (
-// !\A[3]~input_o & ( !\adder_unit|OUT_1 [3] & ( \B[3]~input_o ) ) )
+// \adder_unit|OUT_CIN [0] = ( \A[3]~input_o & ( !\B[3]~input_o $ (\adder_unit|OUT_1 [3]) ) ) # ( !\A[3]~input_o & ( !\B[3]~input_o $ (!\adder_unit|OUT_1 [3]) ) )
- .dataa(gnd),
- .datab(!\B[3]~input_o ),
- .datac(gnd),
+ .dataa(!\B[3]~input_o ),
+ .datab(gnd),
+ .datac(!\adder_unit|OUT_1 [3]),
.datad(gnd),
- .datae(!\A[3]~input_o ),
- .dataf(!\adder_unit|OUT_1 [3]),
+ .datae(gnd),
+ .dataf(!\A[3]~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
@@ -681,11 +826,182 @@ cyclonev_lcell_comb \adder_unit|OUT_CIN[0] (
.shareout());
// synopsys translate_off
defparam \adder_unit|OUT_CIN[0] .extended_lut = "off";
-defparam \adder_unit|OUT_CIN[0] .lut_mask = 64'h3333CCCCCCCC3333;
+defparam \adder_unit|OUT_CIN[0] .lut_mask = 64'h5A5A5A5AA5A5A5A5;
defparam \adder_unit|OUT_CIN[0] .shared_arith = "off";
// synopsys translate_on
-// Location: MLABCELL_X8_Y13_N0
+// Location: LABCELL_X53_Y1_N33
+cyclonev_lcell_comb \dut|Mux5~0 (
+// Equation(s):
+// \dut|Mux5~0_combout = ( \Mux0~0_combout & ( (\Mux3~4_combout & (!\Mux2~0_combout $ (!\Mux1~0_combout ))) ) ) # ( !\Mux0~0_combout & ( (!\Mux2~0_combout & (!\Mux1~0_combout $ (!\Mux3~4_combout ))) ) )
+
+ .dataa(!\Mux2~0_combout ),
+ .datab(!\Mux1~0_combout ),
+ .datac(!\Mux3~4_combout ),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(!\Mux0~0_combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\dut|Mux5~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \dut|Mux5~0 .extended_lut = "off";
+defparam \dut|Mux5~0 .lut_mask = 64'h2828282806060606;
+defparam \dut|Mux5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y1_N36
+cyclonev_lcell_comb \dut|Mux4~0 (
+// Equation(s):
+// \dut|Mux4~0_combout = ( \Mux0~0_combout & ( (!\Mux3~4_combout & ((\Mux1~0_combout ))) # (\Mux3~4_combout & (\Mux2~0_combout )) ) ) # ( !\Mux0~0_combout & ( (\Mux1~0_combout & (!\Mux3~4_combout $ (!\Mux2~0_combout ))) ) )
+
+ .dataa(gnd),
+ .datab(!\Mux3~4_combout ),
+ .datac(!\Mux2~0_combout ),
+ .datad(!\Mux1~0_combout ),
+ .datae(gnd),
+ .dataf(!\Mux0~0_combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\dut|Mux4~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \dut|Mux4~0 .extended_lut = "off";
+defparam \dut|Mux4~0 .lut_mask = 64'h003C003C03CF03CF;
+defparam \dut|Mux4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y1_N12
+cyclonev_lcell_comb \dut|Mux3~0 (
+// Equation(s):
+// \dut|Mux3~0_combout = ( \Mux0~0_combout & ( (\Mux1~0_combout & ((!\Mux3~4_combout ) # (\Mux2~0_combout ))) ) ) # ( !\Mux0~0_combout & ( (!\Mux3~4_combout & (\Mux2~0_combout & !\Mux1~0_combout )) ) )
+
+ .dataa(gnd),
+ .datab(!\Mux3~4_combout ),
+ .datac(!\Mux2~0_combout ),
+ .datad(!\Mux1~0_combout ),
+ .datae(gnd),
+ .dataf(!\Mux0~0_combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\dut|Mux3~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \dut|Mux3~0 .extended_lut = "off";
+defparam \dut|Mux3~0 .lut_mask = 64'h0C000C0000CF00CF;
+defparam \dut|Mux3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y1_N21
+cyclonev_lcell_comb \dut|Mux2~0 (
+// Equation(s):
+// \dut|Mux2~0_combout = ( \Mux0~0_combout & ( (!\Mux2~0_combout & (!\Mux1~0_combout & \Mux3~4_combout )) # (\Mux2~0_combout & (!\Mux1~0_combout $ (\Mux3~4_combout ))) ) ) # ( !\Mux0~0_combout & ( (!\Mux2~0_combout & (!\Mux1~0_combout $
+// (!\Mux3~4_combout ))) # (\Mux2~0_combout & (\Mux1~0_combout & \Mux3~4_combout )) ) )
+
+ .dataa(!\Mux2~0_combout ),
+ .datab(!\Mux1~0_combout ),
+ .datac(!\Mux3~4_combout ),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(!\Mux0~0_combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\dut|Mux2~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \dut|Mux2~0 .extended_lut = "off";
+defparam \dut|Mux2~0 .lut_mask = 64'h2929292949494949;
+defparam \dut|Mux2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y1_N54
+cyclonev_lcell_comb \dut|Mux1~0 (
+// Equation(s):
+// \dut|Mux1~0_combout = ( \Mux0~0_combout & ( (\Mux3~4_combout & (!\Mux2~0_combout & !\Mux1~0_combout )) ) ) # ( !\Mux0~0_combout & ( ((!\Mux2~0_combout & \Mux1~0_combout )) # (\Mux3~4_combout ) ) )
+
+ .dataa(gnd),
+ .datab(!\Mux3~4_combout ),
+ .datac(!\Mux2~0_combout ),
+ .datad(!\Mux1~0_combout ),
+ .datae(gnd),
+ .dataf(!\Mux0~0_combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\dut|Mux1~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \dut|Mux1~0 .extended_lut = "off";
+defparam \dut|Mux1~0 .lut_mask = 64'h33F333F330003000;
+defparam \dut|Mux1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y1_N3
+cyclonev_lcell_comb \dut|Mux0~0 (
+// Equation(s):
+// \dut|Mux0~0_combout = ( \Mux0~0_combout & ( (!\Mux2~0_combout & (\Mux1~0_combout & \Mux3~4_combout )) ) ) # ( !\Mux0~0_combout & ( (!\Mux2~0_combout & (!\Mux1~0_combout & \Mux3~4_combout )) # (\Mux2~0_combout & ((!\Mux1~0_combout ) #
+// (\Mux3~4_combout ))) ) )
+
+ .dataa(!\Mux2~0_combout ),
+ .datab(!\Mux1~0_combout ),
+ .datac(!\Mux3~4_combout ),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(!\Mux0~0_combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\dut|Mux0~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \dut|Mux0~0 .extended_lut = "off";
+defparam \dut|Mux0~0 .lut_mask = 64'h4D4D4D4D02020202;
+defparam \dut|Mux0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y1_N6
+cyclonev_lcell_comb \dut|WideOr0~0 (
+// Equation(s):
+// \dut|WideOr0~0_combout = ( \Mux0~0_combout & ( ((!\Mux1~0_combout ) # (\Mux2~0_combout )) # (\Mux3~4_combout ) ) ) # ( !\Mux0~0_combout & ( (!\Mux2~0_combout & ((\Mux1~0_combout ))) # (\Mux2~0_combout & ((!\Mux3~4_combout ) # (!\Mux1~0_combout ))) )
+// )
+
+ .dataa(gnd),
+ .datab(!\Mux3~4_combout ),
+ .datac(!\Mux2~0_combout ),
+ .datad(!\Mux1~0_combout ),
+ .datae(gnd),
+ .dataf(!\Mux0~0_combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\dut|WideOr0~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \dut|WideOr0~0 .extended_lut = "off";
+defparam \dut|WideOr0~0 .lut_mask = 64'h0FFC0FFCFF3FFF3F;
+defparam \dut|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X27_Y18_N3
cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
// Equation(s):
diff --git a/modules/alu.sv b/modules/alu.sv
index 2687745..448fd0c 100644
--- a/modules/alu.sv
+++ b/modules/alu.sv
@@ -3,12 +3,14 @@
`include "asu.sv"
`include "lu.sv"
+`include "seven_seg.sv"
// flags[0:0] = Cout
// flags[1:1] = Overflow
module alu #(parameter width=2)(input logic [3:0] op,
input logic [2**width-1:0] A, input logic [2**width-1:0] B,
- output logic [2**width-1:0] OUT_1, output logic[1:0] flags);
+ output logic [2**width-1:0] OUT_1, output logic[1:0] flags,
+ output logic [7:0] out_seg1);
logic [0:0] asu_op;
logic [2**width-1:0] asu_out;
@@ -33,5 +35,6 @@ module alu #(parameter width=2)(input logic [3:0] op,
default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
endcase
end
+ seven_seg dut(OUT_1, 1, out_seg1);
endmodule
`endif
\ No newline at end of file