Merge branch 'main' of https://git.rileyk.au/TroubleElectrical/FPGA_Uni

Quartus/A1_Q6/db/instruction_classifier.db_info

@@ -1,3 +1,3 @@
 Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Version_Index = 604268800
-Creation_Time = Tue Sep 15 19:51:34 2026
+Creation_Time = Thu Sep 24 15:45:52 2026

Quartus/A1_Q6/db/instruction_classifier.tmw_info

@@ -1,7 +1,4 @@
-start_full_compilation:s:00:00:58
-start_analysis_synthesis:s:00:00:13-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:29-start_full_compilation
-start_assembler:s:00:00:07-start_full_compilation
-start_timing_analyzer:s:00:00:07-start_full_compilation
-start_eda_netlist_writer:s:00:00:02-start_full_compilation
+start_full_compilation:s
+start_assembler:s-start_full_compilation
+start_timing_analyzer:s-start_full_compilation
+start_eda_netlist_writer:s-start_full_compilation

modules/register_file.sv

@@ -1,22 +1,22 @@
 `ifndef REGISTER_FILE_H
 `define REGISTER_FILE_H
 
-module register_file #(parameter width=5, parameter nregs=16)(
+module register_file #(parameter width=5, parameter nregs=32)(
     input logic [0:0] clk, input logic[0:0] we,
-    input logic [$clog(nregs)-1:0] A_W1, input logic [2**width-1:0] W1,
-    input logic [$clog(nregs)-1:0] A_R1, output logic [2**width-1:0] R1,
-    input logic [$clog(nregs)-1:0] A_R2, output logic [2**width-1:0] R2
+    input logic [$clog(nregs)-1:0] WA, input logic [2**width-1:0] WD,
+    input logic [$clog(nregs)-1:0] RA1, output logic [2**width-1:0] RD1,
+    input logic [$clog(nregs)-1:0] RA2, output logic [2**width-1:0] RD2
 );
     localparam BW = 2**width;
     logic [2**width-1:0] regs[nregs];
 
     always_ff @(posedge clk) begin
-        if (we & (A_W1 != {(2**width){1'b0}} )) begin
-            regs[A_W1] <= W1;
+        if (we & (WA != {(2**width){1'b0}} )) begin
+            regs[WA] <= WD;
         end
     end
 
-    assign R1 = regs[A_R1];
-    assign R2 = regs[A_R2];
+    assign RD1 = regs[RA1];
+    assign RD2 = regs[RA2];
 endmodule
 `endif