From b49e294b7d93a8b0b333e909a10997061d2cef22 Mon Sep 17 00:00:00 2001 From: TroubleElectrical Date: Thu, 8 Oct 2026 15:04:38 +1100 Subject: [PATCH] Updated register_file.sv with proper naming scheme and 32bit width --- .../A1_Q6/db/instruction_classifier.db_info | 2 +- .../A1_Q6/db/instruction_classifier.tmw_info | 11 ++++------- Quartus/A1_Q6/instruction_classifier.qws | Bin 762 -> 48 bytes modules/register_file.sv | 18 +++++++++--------- 4 files changed, 14 insertions(+), 17 deletions(-) diff --git a/Quartus/A1_Q6/db/instruction_classifier.db_info b/Quartus/A1_Q6/db/instruction_classifier.db_info index 94c2229..74f4ad0 100644 --- a/Quartus/A1_Q6/db/instruction_classifier.db_info +++ b/Quartus/A1_Q6/db/instruction_classifier.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Version_Index = 604268800 -Creation_Time = Tue Sep 15 19:51:34 2026 +Creation_Time = Thu Sep 24 15:45:52 2026 diff --git a/Quartus/A1_Q6/db/instruction_classifier.tmw_info b/Quartus/A1_Q6/db/instruction_classifier.tmw_info index d42c07f..1bd50f7 100644 --- a/Quartus/A1_Q6/db/instruction_classifier.tmw_info +++ b/Quartus/A1_Q6/db/instruction_classifier.tmw_info @@ -1,7 +1,4 @@ -start_full_compilation:s:00:00:58 -start_analysis_synthesis:s:00:00:13-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:29-start_full_compilation -start_assembler:s:00:00:07-start_full_compilation -start_timing_analyzer:s:00:00:07-start_full_compilation -start_eda_netlist_writer:s:00:00:02-start_full_compilation +start_full_compilation:s +start_assembler:s-start_full_compilation +start_timing_analyzer:s-start_full_compilation +start_eda_netlist_writer:s-start_full_compilation diff --git a/Quartus/A1_Q6/instruction_classifier.qws b/Quartus/A1_Q6/instruction_classifier.qws index ea2bb2059b3167e58fa118132787b30a01f061bc..63563b76eda4b19c3f4f321afd3f1b7df67b8d5e 100644 GIT binary patch delta 11 PcmeyxYA`{Yl>r0*5_SRb literal 762 zcmb`Ey-EX75QWbgg_KrS7AZu6u!%n#jhzHc6)ePFbiJ!fOg3!d4~UJWPvQI6*xLIT zO8n-sYY{|HoXgzVnR{mD%dxx>P%PU zIgm}I8v6X4SWKOi_aW8dqVkwXf;wt9KwcMBd%6R&MW;<}hjj|QA8VbjNG-L|P`mUq zT&Qg-CA{w7nMP<^8@m60mNt0s$TdavVV6{C5q#idzR)VR`d&B~&7rI6F-yWOYU;3+ z3CDI)(-AgfFQ@R%4XP<(wva`2Np%ctkXZfiK%N>2bse(Tb6xzUlNB~y@uWsSQ}yg- zs4kJ{bnAQXLpb$Q=0*`;ML9_2pSs>`N*Um7hx27@C-Gvn{-p JFZ?=>`~=H6eoFuV diff --git a/modules/register_file.sv b/modules/register_file.sv index 85cfa04..971e9c2 100644 --- a/modules/register_file.sv +++ b/modules/register_file.sv @@ -1,22 +1,22 @@ `ifndef REGISTER_FILE_H `define REGISTER_FILE_H -module register_file #(parameter width=5, parameter nregs=16)( +module register_file #(parameter width=5, parameter nregs=32)( input logic [0:0] clk, input logic[0:0] we, - input logic [$clog(nregs)-1:0] A_W1, input logic [2**width-1:0] W1, - input logic [$clog(nregs)-1:0] A_R1, output logic [2**width-1:0] R1, - input logic [$clog(nregs)-1:0] A_R2, output logic [2**width-1:0] R2 + input logic [$clog(nregs)-1:0] WA, input logic [2**width-1:0] WD, + input logic [$clog(nregs)-1:0] RA1, output logic [2**width-1:0] RD1, + input logic [$clog(nregs)-1:0] RA2, output logic [2**width-1:0] RD2 ); localparam BW = 2**width; logic [2**width-1:0] regs[nregs]; always_ff @(posedge clk) begin - if (we & (A_W1 != {(2**width){1'b0}} )) begin - regs[A_W1] <= W1; + if (we & (WA != {(2**width){1'b0}} )) begin + regs[WA] <= WD; end end - assign R1 = regs[A_R1]; - assign R2 = regs[A_R2]; + assign RD1 = regs[RA1]; + assign RD2 = regs[RA2]; endmodule -`endif \ No newline at end of file +`endif