Added ModelSim folder (and have to add files into it as to allow for different testbench code)
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; Copyright 1991-2009 Mentor Graphics Corporation
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;
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; All Rights Reserved.
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;
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; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
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; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
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;
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[Library]
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std = $MODEL_TECH/../std
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ieee = $MODEL_TECH/../ieee
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verilog = $MODEL_TECH/../verilog
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vital2000 = $MODEL_TECH/../vital2000
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std_developerskit = $MODEL_TECH/../std_developerskit
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synopsys = $MODEL_TECH/../synopsys
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modelsim_lib = $MODEL_TECH/../modelsim_lib
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sv_std = $MODEL_TECH/../sv_std
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; Altera Primitive libraries
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;
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; VHDL Section
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;
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altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
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altera = $MODEL_TECH/../altera/vhdl/altera
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altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
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lpm = $MODEL_TECH/../altera/vhdl/220model
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220model = $MODEL_TECH/../altera/vhdl/220model
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maxii = $MODEL_TECH/../altera/vhdl/maxii
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maxv = $MODEL_TECH/../altera/vhdl/maxv
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fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
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sgate = $MODEL_TECH/../altera/vhdl/sgate
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arriaii = $MODEL_TECH/../altera/vhdl/arriaii
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arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
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arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
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arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
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arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
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arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
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stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
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stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
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stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
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cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
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cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
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cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
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cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
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stratixv = $MODEL_TECH/../altera/vhdl/stratixv
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stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
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stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
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arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
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arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
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arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
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arriav = $MODEL_TECH/../altera/vhdl/arriav
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cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
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twentynm = $MODEL_TECH/../altera/vhdl/twentynm
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twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
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twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
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cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp
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;
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; Verilog Section
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;
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altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
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altera_ver = $MODEL_TECH/../altera/verilog/altera
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altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
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lpm_ver = $MODEL_TECH/../altera/verilog/220model
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220model_ver = $MODEL_TECH/../altera/verilog/220model
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maxii_ver = $MODEL_TECH/../altera/verilog/maxii
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maxv_ver = $MODEL_TECH/../altera/verilog/maxv
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fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
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sgate_ver = $MODEL_TECH/../altera/verilog/sgate
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arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
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arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
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arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
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arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
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arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
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arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
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stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
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stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
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stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
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stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
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stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
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stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
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arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
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arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
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arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
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arriav_ver = $MODEL_TECH/../altera/verilog/arriav
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arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
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arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
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cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
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cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
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cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
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cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
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cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
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cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
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cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
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twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
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twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
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twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
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cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp
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work = work
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[vcom]
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; VHDL93 variable selects language version as the default.
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; Default is VHDL-2002.
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; Value of 0 or 1987 for VHDL-1987.
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; Value of 1 or 1993 for VHDL-1993.
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; Default or value of 2 or 2002 for VHDL-2002.
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; Default or value of 3 or 2008 for VHDL-2008.
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VHDL93 = 2002
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||||||
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; Show source line containing error. Default is off.
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||||||
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; Show_source = 1
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||||||
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; Turn off unbound-component warnings. Default is on.
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||||||
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; Show_Warning1 = 0
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||||||
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||||||
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; Turn off process-without-a-wait-statement warnings. Default is on.
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; Show_Warning2 = 0
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||||||
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||||||
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; Turn off null-range warnings. Default is on.
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||||||
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; Show_Warning3 = 0
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||||||
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||||||
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; Turn off no-space-in-time-literal warnings. Default is on.
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||||||
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; Show_Warning4 = 0
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||||||
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||||||
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; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
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; Show_Warning5 = 0
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||||||
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||||||
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; Turn off optimization for IEEE std_logic_1164 package. Default is on.
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||||||
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; Optimize_1164 = 0
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||||||
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||||||
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; Turn on resolving of ambiguous function overloading in favor of the
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||||||
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; "explicit" function declaration (not the one automatically created by
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||||||
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; the compiler for each type declaration). Default is off.
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||||||
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; The .ini file has Explicit enabled so that std_logic_signed/unsigned
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; will match the behavior of synthesis tools.
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Explicit = 1
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||||||
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; Turn off acceleration of the VITAL packages. Default is to accelerate.
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||||||
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; NoVital = 1
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||||||
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||||||
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; Turn off VITAL compliance checking. Default is checking on.
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||||||
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; NoVitalCheck = 1
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||||||
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||||||
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; Ignore VITAL compliance checking errors. Default is to not ignore.
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||||||
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; IgnoreVitalErrors = 1
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||||||
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||||||
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; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
||||||
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; Show_VitalChecksWarnings = 0
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||||||
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||||||
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; Keep silent about case statement static warnings.
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||||||
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; Default is to give a warning.
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||||||
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; NoCaseStaticError = 1
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||||||
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||||||
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; Keep silent about warnings caused by aggregates that are not locally static.
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||||||
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; Default is to give a warning.
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||||||
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; NoOthersStaticError = 1
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||||||
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||||||
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; Turn off inclusion of debugging info within design units.
|
||||||
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; Default is to include debugging info.
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||||||
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; NoDebug = 1
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||||||
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||||||
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; Turn off "Loading..." messages. Default is messages on.
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||||||
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; Quiet = 1
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||||||
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||||||
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; Turn on some limited synthesis rule compliance checking. Checks only:
|
||||||
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; -- signals used (read) by a process must be in the sensitivity list
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||||||
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; CheckSynthesis = 1
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||||||
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||||||
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; Activate optimizations on expressions that do not involve signals,
|
||||||
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; waits, or function/procedure/task invocations. Default is off.
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||||||
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; ScalarOpts = 1
|
||||||
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|
||||||
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; Require the user to specify a configuration for all bindings,
|
||||||
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; and do not generate a compile time default binding for the
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||||||
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; component. This will result in an elaboration error of
|
||||||
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; 'component not bound' if the user fails to do so. Avoids the rare
|
||||||
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; issue of a false dependency upon the unused default binding.
|
||||||
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; RequireConfigForAllDefaultBinding = 1
|
||||||
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|
||||||
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; Inhibit range checking on subscripts of arrays. Range checking on
|
||||||
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; scalars defined with subtypes is inhibited by default.
|
||||||
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; NoIndexCheck = 1
|
||||||
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|
||||||
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; Inhibit range checks on all (implicit and explicit) assignments to
|
||||||
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; scalar objects defined with subtypes.
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||||||
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; NoRangeCheck = 1
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||||||
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[vlog]
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||||||
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|
||||||
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; Turn off inclusion of debugging info within design units.
|
||||||
|
; Default is to include debugging info.
|
||||||
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; NoDebug = 1
|
||||||
|
|
||||||
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; Turn off "loading..." messages. Default is messages on.
|
||||||
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; Quiet = 1
|
||||||
|
|
||||||
|
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
||||||
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; Default is off.
|
||||||
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; Hazard = 1
|
||||||
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|
||||||
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; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
||||||
|
; insensitivity for module names. Default is no conversion.
|
||||||
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; UpCase = 1
|
||||||
|
|
||||||
|
; Turn on incremental compilation of modules. Default is off.
|
||||||
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; Incremental = 1
|
||||||
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|
||||||
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; Turns on lint-style checking.
|
||||||
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; Show_Lint = 1
|
||||||
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[vsim]
|
||||||
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; Simulator resolution
|
||||||
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; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
||||||
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Resolution = ps
|
||||||
|
|
||||||
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; User time unit for run commands
|
||||||
|
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
||||||
|
; unit specified for Resolution. For example, if Resolution is 100ps,
|
||||||
|
; then UserTimeUnit defaults to ps.
|
||||||
|
; Should generally be set to default.
|
||||||
|
UserTimeUnit = default
|
||||||
|
|
||||||
|
; Default run length
|
||||||
|
RunLength = 100 ps
|
||||||
|
|
||||||
|
; Maximum iterations that can be run without advancing simulation time
|
||||||
|
IterationLimit = 5000
|
||||||
|
|
||||||
|
; Directive to license manager:
|
||||||
|
; vhdl Immediately reserve a VHDL license
|
||||||
|
; vlog Immediately reserve a Verilog license
|
||||||
|
; plus Immediately reserve a VHDL and Verilog license
|
||||||
|
; nomgc Do not look for Mentor Graphics Licenses
|
||||||
|
; nomti Do not look for Model Technology Licenses
|
||||||
|
; noqueue Do not wait in the license queue when a license isn't available
|
||||||
|
; viewsim Try for viewer license but accept simulator license(s) instead
|
||||||
|
; of queuing for viewer license
|
||||||
|
; License = plus
|
||||||
|
|
||||||
|
; Stop the simulator after a VHDL/Verilog assertion message
|
||||||
|
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||||
|
BreakOnAssertion = 3
|
||||||
|
|
||||||
|
; Assertion Message Format
|
||||||
|
; %S - Severity Level
|
||||||
|
; %R - Report Message
|
||||||
|
; %T - Time of assertion
|
||||||
|
; %D - Delta
|
||||||
|
; %I - Instance or Region pathname (if available)
|
||||||
|
; %% - print '%' character
|
||||||
|
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||||
|
|
||||||
|
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
|
||||||
|
; AssertFile = assert.log
|
||||||
|
|
||||||
|
; Default radix for all windows and commands...
|
||||||
|
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
||||||
|
DefaultRadix = symbolic
|
||||||
|
|
||||||
|
; VSIM Startup command
|
||||||
|
; Startup = do startup.do
|
||||||
|
|
||||||
|
; File for saving command transcript
|
||||||
|
TranscriptFile = transcript
|
||||||
|
|
||||||
|
; File for saving command history
|
||||||
|
; CommandHistory = cmdhist.log
|
||||||
|
|
||||||
|
; Specify whether paths in simulator commands should be described
|
||||||
|
; in VHDL or Verilog format.
|
||||||
|
; For VHDL, PathSeparator = /
|
||||||
|
; For Verilog, PathSeparator = .
|
||||||
|
; Must not be the same character as DatasetSeparator.
|
||||||
|
PathSeparator = /
|
||||||
|
|
||||||
|
; Specify the dataset separator for fully rooted contexts.
|
||||||
|
; The default is ':'. For example, sim:/top
|
||||||
|
; Must not be the same character as PathSeparator.
|
||||||
|
DatasetSeparator = :
|
||||||
|
|
||||||
|
; Disable VHDL assertion messages
|
||||||
|
; IgnoreNote = 1
|
||||||
|
; IgnoreWarning = 1
|
||||||
|
; IgnoreError = 1
|
||||||
|
; IgnoreFailure = 1
|
||||||
|
|
||||||
|
; Default force kind. May be freeze, drive, deposit, or default
|
||||||
|
; or in other terms, fixed, wired, or charged.
|
||||||
|
; A value of "default" will use the signal kind to determine the
|
||||||
|
; force kind, drive for resolved signals, freeze for unresolved signals
|
||||||
|
; DefaultForceKind = freeze
|
||||||
|
|
||||||
|
; If zero, open files when elaborated; otherwise, open files on
|
||||||
|
; first read or write. Default is 0.
|
||||||
|
; DelayFileOpen = 1
|
||||||
|
|
||||||
|
; Control VHDL files opened for write.
|
||||||
|
; 0 = Buffered, 1 = Unbuffered
|
||||||
|
UnbufferedOutput = 0
|
||||||
|
|
||||||
|
; Control the number of VHDL files open concurrently.
|
||||||
|
; This number should always be less than the current ulimit
|
||||||
|
; setting for max file descriptors.
|
||||||
|
; 0 = unlimited
|
||||||
|
ConcurrentFileLimit = 40
|
||||||
|
|
||||||
|
; Control the number of hierarchical regions displayed as
|
||||||
|
; part of a signal name shown in the Wave window.
|
||||||
|
; A value of zero tells VSIM to display the full name.
|
||||||
|
; The default is 0.
|
||||||
|
; WaveSignalNameWidth = 0
|
||||||
|
|
||||||
|
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
||||||
|
; and std_logic_signed packages.
|
||||||
|
; StdArithNoWarnings = 1
|
||||||
|
|
||||||
|
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
||||||
|
; NumericStdNoWarnings = 1
|
||||||
|
|
||||||
|
; Control the format of the (VHDL) FOR generate statement label
|
||||||
|
; for each iteration. Do not quote it.
|
||||||
|
; The format string here must contain the conversion codes %s and %d,
|
||||||
|
; in that order, and no other conversion codes. The %s represents
|
||||||
|
; the generate_label; the %d represents the generate parameter value
|
||||||
|
; at a particular generate iteration (this is the position number if
|
||||||
|
; the generate parameter is of an enumeration type). Embedded whitespace
|
||||||
|
; is allowed (but discouraged); leading and trailing whitespace is ignored.
|
||||||
|
; Application of the format must result in a unique scope name over all
|
||||||
|
; such names in the design so that name lookup can function properly.
|
||||||
|
; GenerateFormat = %s__%d
|
||||||
|
|
||||||
|
; Specify whether checkpoint files should be compressed.
|
||||||
|
; The default is 1 (compressed).
|
||||||
|
; CheckpointCompressMode = 0
|
||||||
|
|
||||||
|
; List of dynamically loaded objects for Verilog PLI applications
|
||||||
|
; Veriuser = veriuser.sl
|
||||||
|
|
||||||
|
; Specify default options for the restart command. Options can be one
|
||||||
|
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
||||||
|
; DefaultRestartOptions = -force
|
||||||
|
|
||||||
|
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
||||||
|
; (> 500 megabyte memory footprint). Default is disabled.
|
||||||
|
; Specify number of megabytes to lock.
|
||||||
|
; LockedMemory = 1000
|
||||||
|
|
||||||
|
; Turn on (1) or off (0) WLF file compression.
|
||||||
|
; The default is 1 (compress WLF file).
|
||||||
|
; WLFCompress = 0
|
||||||
|
|
||||||
|
; Specify whether to save all design hierarchy (1) in the WLF file
|
||||||
|
; or only regions containing logged signals (0).
|
||||||
|
; The default is 0 (save only regions with logged signals).
|
||||||
|
; WLFSaveAllRegions = 1
|
||||||
|
|
||||||
|
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
||||||
|
; to the specified amount of simulation time. When the limit is exceeded
|
||||||
|
; the earliest times get truncated from the file.
|
||||||
|
; If both time and size limits are specified the most restrictive is used.
|
||||||
|
; UserTimeUnits are used if time units are not specified.
|
||||||
|
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
||||||
|
; WLFTimeLimit = 0
|
||||||
|
|
||||||
|
; WLF file size limit. Limit WLF file size, as closely as possible,
|
||||||
|
; to the specified number of megabytes. If both time and size limits
|
||||||
|
; are specified then the most restrictive is used.
|
||||||
|
; The default is 0 (no limit).
|
||||||
|
; WLFSizeLimit = 1000
|
||||||
|
|
||||||
|
; Specify whether or not a WLF file should be deleted when the
|
||||||
|
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
||||||
|
; The default is 0 (do not delete WLF file when simulation ends).
|
||||||
|
; WLFDeleteOnQuit = 1
|
||||||
|
|
||||||
|
; Automatic SDF compilation
|
||||||
|
; Disables automatic compilation of SDF files in flows that support it.
|
||||||
|
; Default is on, uncomment to turn off.
|
||||||
|
; NoAutoSDFCompile = 1
|
||||||
|
|
||||||
|
[lmc]
|
||||||
|
|
||||||
|
[msg_system]
|
||||||
|
; Change a message severity or suppress a message.
|
||||||
|
; The format is: <msg directive> = <msg number>[,<msg number>...]
|
||||||
|
; Examples:
|
||||||
|
; note = 3009
|
||||||
|
; warning = 3033
|
||||||
|
; error = 3010,3016
|
||||||
|
; fatal = 3016,3033
|
||||||
|
; suppress = 3009,3016,3043
|
||||||
|
; The command verror <msg number> can be used to get the complete
|
||||||
|
; description of a message.
|
||||||
|
|
||||||
|
; Control transcripting of elaboration/runtime messages.
|
||||||
|
; The default is to have messages appear in the transcript and
|
||||||
|
; recorded in the wlf file (messages that are recorded in the
|
||||||
|
; wlf file can be viewed in the MsgViewer). The other settings
|
||||||
|
; are to send messages only to the transcript or only to the
|
||||||
|
; wlf file. The valid values are
|
||||||
|
; both {default}
|
||||||
|
; tran {transcript only}
|
||||||
|
; wlf {wlf file only}
|
||||||
|
; msgmode = both
|
||||||
|
[Project]
|
||||||
|
** Warning: ; Warning -- Do not edit the project properties directly.
|
||||||
|
; Property names are dynamic in nature and property
|
||||||
|
; values have special syntax. Changing property data directly
|
||||||
|
; can result in a corrupt MPF file. All project properties
|
||||||
|
; can be modified through project window dialogs.
|
||||||
|
Project_Version = 6
|
||||||
|
Project_DefaultLib = work
|
||||||
|
Project_SortMethod = unused
|
||||||
|
Project_Files_Count = 2
|
||||||
|
Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
|
||||||
|
Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1788845636 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||||
|
Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
|
||||||
|
Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1788848626 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||||
|
Project_Sim_Count = 0
|
||||||
|
Project_Folder_Count = 0
|
||||||
|
Echo_Compile_Output = 0
|
||||||
|
Save_Compile_Report = 1
|
||||||
|
Project_Opt_Count = 0
|
||||||
|
ForceSoftPaths = 0
|
||||||
|
ProjectStatusDelay = 5000
|
||||||
|
VERILOG_DoubleClick = Edit
|
||||||
|
VERILOG_CustomDoubleClick =
|
||||||
|
SYSTEMVERILOG_DoubleClick = Edit
|
||||||
|
SYSTEMVERILOG_CustomDoubleClick =
|
||||||
|
VHDL_DoubleClick = Edit
|
||||||
|
VHDL_CustomDoubleClick =
|
||||||
|
PSL_DoubleClick = Edit
|
||||||
|
PSL_CustomDoubleClick =
|
||||||
|
TEXT_DoubleClick = Edit
|
||||||
|
TEXT_CustomDoubleClick =
|
||||||
|
SYSTEMC_DoubleClick = Edit
|
||||||
|
SYSTEMC_CustomDoubleClick =
|
||||||
|
TCL_DoubleClick = Edit
|
||||||
|
TCL_CustomDoubleClick =
|
||||||
|
MACRO_DoubleClick = Edit
|
||||||
|
MACRO_CustomDoubleClick =
|
||||||
|
VCD_DoubleClick = Edit
|
||||||
|
VCD_CustomDoubleClick =
|
||||||
|
SDF_DoubleClick = Edit
|
||||||
|
SDF_CustomDoubleClick =
|
||||||
|
XML_DoubleClick = Edit
|
||||||
|
XML_CustomDoubleClick =
|
||||||
|
LOGFILE_DoubleClick = Edit
|
||||||
|
LOGFILE_CustomDoubleClick =
|
||||||
|
UCDB_DoubleClick = Edit
|
||||||
|
UCDB_CustomDoubleClick =
|
||||||
|
TDB_DoubleClick = Edit
|
||||||
|
TDB_CustomDoubleClick =
|
||||||
|
UPF_DoubleClick = Edit
|
||||||
|
UPF_CustomDoubleClick =
|
||||||
|
PCF_DoubleClick = Edit
|
||||||
|
PCF_CustomDoubleClick =
|
||||||
|
PROJECT_DoubleClick = Edit
|
||||||
|
PROJECT_CustomDoubleClick =
|
||||||
|
VRM_DoubleClick = Edit
|
||||||
|
VRM_CustomDoubleClick =
|
||||||
|
DEBUGDATABASE_DoubleClick = Edit
|
||||||
|
DEBUGDATABASE_CustomDoubleClick =
|
||||||
|
DEBUGARCHIVE_DoubleClick = Edit
|
||||||
|
DEBUGARCHIVE_CustomDoubleClick =
|
||||||
|
Project_Major_Version = 2020
|
||||||
|
Project_Minor_Version = 1
|
||||||
@@ -0,0 +1,16 @@
|
|||||||
|
module lu #(parameter width = 2) (
|
||||||
|
input logic [1:0] op,
|
||||||
|
input logic [2**width-1:0] A,
|
||||||
|
input logic [2**width-1:0] B,
|
||||||
|
output logic [2**width-1:0] Y);
|
||||||
|
|
||||||
|
always_comb begin
|
||||||
|
case (op)
|
||||||
|
2'b00: Y = A & B;
|
||||||
|
2'b01: Y = A | B;
|
||||||
|
2'b10: Y = A ^ B;
|
||||||
|
2'b11: Y = ~(A | B);
|
||||||
|
default: Y = '0;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,59 @@
|
|||||||
|
`include "lu.sv"
|
||||||
|
|
||||||
|
module lu_tb #(W=4)();
|
||||||
|
logic [1:0] op;
|
||||||
|
logic [W-1:0] A;
|
||||||
|
logic [W-1:0] B;
|
||||||
|
logic [W-1:0] C;
|
||||||
|
logic [W-1:0] C_exp[16];
|
||||||
|
|
||||||
|
lu #(W) dut();
|
||||||
|
|
||||||
|
integer error_count;
|
||||||
|
initial begin
|
||||||
|
// AND
|
||||||
|
C_exp[0] = {W{1'b0}};
|
||||||
|
C_exp[1] = {W{1'b0}};
|
||||||
|
C_exp[2] = {W{1'b0}};
|
||||||
|
C_exp[3] = {W{1'b0}};
|
||||||
|
// OR
|
||||||
|
C_exp[4] = {W{1'b0}};
|
||||||
|
C_exp[5] = {W{1'b1}};
|
||||||
|
C_exp[6] = {W{1'b1}};
|
||||||
|
C_exp[7] = {W{1'b1}};
|
||||||
|
// XOR
|
||||||
|
C_exp[8] = {W{1'b0}};
|
||||||
|
C_exp[9] = {W{1'b1}};
|
||||||
|
C_exp[10] = {W{1'b1}};
|
||||||
|
C_exp[11] = {W{1'b0}};
|
||||||
|
// NOR
|
||||||
|
C_exp[12] = {W{1'b1}};
|
||||||
|
C_exp[13] = {W{1'b0}};
|
||||||
|
C_exp[14] = {W{1'b0}};
|
||||||
|
C_exp[15] = {W{1'b0}};
|
||||||
|
|
||||||
|
error_count = 0;
|
||||||
|
op = 0;
|
||||||
|
A = 0;
|
||||||
|
B = 0;
|
||||||
|
$display("Beginning LU tests");
|
||||||
|
for (integer N = 0; N < 4; ++N) begin
|
||||||
|
for (integer M = 0; M < 2; ++M) begin
|
||||||
|
for (integer K = 0; K < 2; ++K) begin
|
||||||
|
#1;
|
||||||
|
if (C != C_exp[N*2*2 + M*2 + K]) begin
|
||||||
|
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", op, A, B, C, C_exp[N*2*2 + M*2 + K]);
|
||||||
|
error_count = error_count + 1;
|
||||||
|
end
|
||||||
|
B = 1;
|
||||||
|
end
|
||||||
|
A = 1;
|
||||||
|
end
|
||||||
|
A = 0;
|
||||||
|
B = 0;
|
||||||
|
op = op + 1;
|
||||||
|
end
|
||||||
|
if (error_count == 0) $display("\x1b[38;5;10mAll LU tests passing\x1b[m");
|
||||||
|
else $display("\x1b[38;5;9m%0d LU test(s) failing\x1b[m", error_count);
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,46 @@
|
|||||||
|
# Loading project Assignment_1_Q2
|
||||||
|
# Compile of lu.sv was successful.
|
||||||
|
# Compile of lu_tb.sv failed with 1 errors.
|
||||||
|
# 2 compiles, 1 failed with 1 error.
|
||||||
|
# Compile of lu_tb.sv failed with 1 errors.
|
||||||
|
# Compile of lu.sv was successful.
|
||||||
|
# Compile of lu_tb.sv was successful.
|
||||||
|
# 2 compiles, 0 failed with no errors.
|
||||||
|
vsim work.lu_tb
|
||||||
|
# vsim work.lu_tb
|
||||||
|
# Start time: 16:26:37 on Sep 08,2026
|
||||||
|
# Loading sv_std.std
|
||||||
|
# Loading work.lu_tb
|
||||||
|
# Loading work.lu
|
||||||
|
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'dut'. Expected 4, found 0.
|
||||||
|
# Time: 0 ps Iteration: 0 Instance: /lu_tb/dut File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv Line: 10
|
||||||
|
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'op'.
|
||||||
|
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'A'.
|
||||||
|
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'B'.
|
||||||
|
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'Y'.
|
||||||
|
add wave -position end sim:/lu_tb/op
|
||||||
|
add wave -position end sim:/lu_tb/A
|
||||||
|
add wave -position end sim:/lu_tb/A
|
||||||
|
add wave -position end sim:/lu_tb/B
|
||||||
|
add wave -position end sim:/lu_tb/C
|
||||||
|
quit -sim
|
||||||
|
# End time: 16:28:07 on Sep 08,2026, Elapsed time: 0:01:30
|
||||||
|
# Errors: 0, Warnings: 12
|
||||||
|
# Compile of lu.sv was successful.
|
||||||
|
# Compile of lu_tb.sv was successful.
|
||||||
|
# 2 compiles, 0 failed with no errors.
|
||||||
|
vsim work.lu_tb
|
||||||
|
# vsim work.lu_tb
|
||||||
|
# Start time: 16:30:51 on Sep 08,2026
|
||||||
|
# Loading sv_std.std
|
||||||
|
# Loading work.lu_tb
|
||||||
|
# Loading work.lu
|
||||||
|
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'dut'. Expected 4, found 0.
|
||||||
|
# Time: 0 ps Iteration: 0 Instance: /lu_tb/dut File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv Line: 10
|
||||||
|
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'op'.
|
||||||
|
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'A'.
|
||||||
|
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'B'.
|
||||||
|
# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'Y'.
|
||||||
|
quit -sim
|
||||||
|
# End time: 16:31:17 on Sep 08,2026, Elapsed time: 0:00:26
|
||||||
|
# Errors: 0, Warnings: 7
|
||||||
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@@ -0,0 +1,61 @@
|
|||||||
|
m255
|
||||||
|
K4
|
||||||
|
z2
|
||||||
|
!s11f vlog 2020.1 2020.02, Feb 28 2020
|
||||||
|
13
|
||||||
|
!s112 1.1
|
||||||
|
!i10d 8192
|
||||||
|
!i10e 25
|
||||||
|
!i10f 100
|
||||||
|
cModel Technology
|
||||||
|
d/home/oliver/intelFPGA/20.1/modelsim_ase/bin
|
||||||
|
vlu
|
||||||
|
Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3
|
||||||
|
Z1 !s110 1788849038
|
||||||
|
!i10b 1
|
||||||
|
!s100 nmDP9zlMCJDa@W3_FY5m[2
|
||||||
|
Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1
|
||||||
|
Il^hWCV0VAo9mz6NG=G9=51
|
||||||
|
Z3 VDg1SIo80bB@j0V0VzS_@n1
|
||||||
|
S1
|
||||||
|
Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim
|
||||||
|
w1788845636
|
||||||
|
8lu.sv
|
||||||
|
Flu.sv
|
||||||
|
!i122 6
|
||||||
|
L0 1 16
|
||||||
|
Z5 OV;L;2020.1;71
|
||||||
|
r1
|
||||||
|
!s85 0
|
||||||
|
31
|
||||||
|
Z6 !s108 1788849037.000000
|
||||||
|
!s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
|
||||||
|
Z7 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
|
||||||
|
!i113 1
|
||||||
|
Z8 o-work work -sv
|
||||||
|
Z9 tCvgOpt 0
|
||||||
|
vlu_tb
|
||||||
|
R0
|
||||||
|
R1
|
||||||
|
!i10b 1
|
||||||
|
!s100 gdCQZUG[6;:5f<I_jIOd?1
|
||||||
|
R2
|
||||||
|
IOAk[D29KmDQ0<F@G9G][k3
|
||||||
|
R3
|
||||||
|
S1
|
||||||
|
R4
|
||||||
|
w1788848626
|
||||||
|
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
|
||||||
|
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
|
||||||
|
!i122 6
|
||||||
|
L0 3 57
|
||||||
|
R5
|
||||||
|
r1
|
||||||
|
!s85 0
|
||||||
|
31
|
||||||
|
R6
|
||||||
|
Z10 !s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
|
||||||
|
R7
|
||||||
|
!i113 1
|
||||||
|
R8
|
||||||
|
R9
|
||||||
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788845159220 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788846115934 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788845159221 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:25:59 2026 " "Processing started: Tue Sep 8 15:25:59 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788845159221 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788845159221 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788846115934 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:41:55 2026 " "Processing started: Tue Sep 8 15:41:55 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788846115934 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788846115934 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q2 -c lu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788845159221 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q2 -c lu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788846115934 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788845159892 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788846116615 ""}
|
||||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788845164360 ""}
|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788846121685 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "513 " "Peak virtual memory: 513 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788845164529 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:26:04 2026 " "Processing ended: Tue Sep 8 15:26:04 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788845164529 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788845164529 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788845164529 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788845164529 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "513 " "Peak virtual memory: 513 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788846121865 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:42:01 2026 " "Processing ended: Tue Sep 8 15:42:01 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788846121865 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788846121865 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788846121865 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788846121865 ""}
|
||||||
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@@ -1,6 +1,6 @@
|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788845172313 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788846130996 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788845172313 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:26:12 2026 " "Processing started: Tue Sep 8 15:26:12 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788845172313 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788845172313 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788846130997 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:42:10 2026 " "Processing started: Tue Sep 8 15:42:10 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788846130997 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788846130997 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q2 -c lu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788845172314 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q2 -c lu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788846130997 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788845173068 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788846131765 ""}
|
||||||
{ "Info" "IWSC_DONE_HDL_GENERATION" "lu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/simulation/questa/ simulation " "Generated file lu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788845173114 ""}
|
{ "Info" "IWSC_DONE_HDL_GENERATION" "lu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/simulation/questa/ simulation " "Generated file lu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788846131827 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788845173146 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:26:13 2026 " "Processing ended: Tue Sep 8 15:26:13 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788845173146 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788845173146 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788845173146 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788845173146 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788846131859 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:42:11 2026 " "Processing ended: Tue Sep 8 15:42:11 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788846131859 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788846131859 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788846131859 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788846131859 ""}
|
||||||
@@ -1,44 +1,44 @@
|
|||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788845129924 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788846086718 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788845129924 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788846086718 ""}
|
||||||
{ "Info" "IMPP_MPP_USER_DEVICE" "lu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"lu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788845129929 ""}
|
{ "Info" "IMPP_MPP_USER_DEVICE" "lu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"lu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788846086722 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788845130010 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788846086797 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788845130010 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788846086797 ""}
|
||||||
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788845130446 ""}
|
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788846087212 ""}
|
||||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788845130477 ""}
|
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788846087239 ""}
|
||||||
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788845130532 ""}
|
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788846087300 ""}
|
||||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788845137531 ""}
|
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788846094476 ""}
|
||||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788845137551 ""}
|
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788846094496 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788845137553 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788846094498 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788845137553 ""}
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788846094498 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788845137553 ""}
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788846094498 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788845137553 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788846094498 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788845137554 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788846094499 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788845137554 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788846094499 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788845137554 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788846094499 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788845137554 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788845137554 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788846094499 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788846094499 ""}
|
||||||
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788845137574 ""}
|
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788846094517 ""}
|
||||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lu.sdc " "Synopsys Design Constraints File file not found: 'lu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788845143638 ""}
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lu.sdc " "Synopsys Design Constraints File file not found: 'lu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788846100702 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788845143639 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788846100702 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788845143639 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788846100703 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788845143640 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788846100703 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788845143640 ""}
|
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788846100704 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788845143641 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788846100704 ""}
|
||||||
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788845143641 ""}
|
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788846100705 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788845143644 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788846100707 ""}
|
||||||
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788845143727 ""}
|
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788846100789 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788845144437 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788846101473 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788845145074 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788846101809 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788845145346 ""}
|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788846102125 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788845145346 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788846102125 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788845145947 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788846102702 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788845151771 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788845151771 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788846108403 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788846108403 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788845152005 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788845152005 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788845152005 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788846108640 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788846108640 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788846108640 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788845152008 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788846108642 ""}
|
||||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788845153127 ""}
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788846109774 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788845153162 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788846109810 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788845153534 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788846110179 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788845153534 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788846110179 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788845154081 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788846110711 ""}
|
||||||
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788845156793 ""}
|
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788846113447 ""}
|
||||||
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1788845157057 ""}
|
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1788846113739 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1342 " "Peak virtual memory: 1342 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788845157620 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:25:57 2026 " "Processing ended: Tue Sep 8 15:25:57 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788845157620 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788845157620 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:40 " "Total CPU time (on all processors): 00:00:40" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788845157620 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788845157620 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1336 " "Peak virtual memory: 1336 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788846114319 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:41:54 2026 " "Processing ended: Tue Sep 8 15:41:54 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788846114319 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788846114319 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:40 " "Total CPU time (on all processors): 00:00:40" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788846114319 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788846114319 ""}
|
||||||
@@ -31,9 +31,9 @@ B[2] => Y.IN1
|
|||||||
B[3] => Y.IN1
|
B[3] => Y.IN1
|
||||||
B[3] => Y.IN1
|
B[3] => Y.IN1
|
||||||
B[3] => Y.IN1
|
B[3] => Y.IN1
|
||||||
Y[0] << Mux3.DB_MAX_OUTPUT_PORT_TYPE
|
Y[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
Y[1] << Mux2.DB_MAX_OUTPUT_PORT_TYPE
|
Y[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
Y[2] << Mux1.DB_MAX_OUTPUT_PORT_TYPE
|
Y[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
Y[3] << Mux0.DB_MAX_OUTPUT_PORT_TYPE
|
Y[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
|
||||||
|
|
||||||
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@@ -1,11 +1,11 @@
|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788845117404 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788846074109 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788845117404 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:25:17 2026 " "Processing started: Tue Sep 8 15:25:17 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788845117404 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788845117404 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788846074109 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:41:13 2026 " "Processing started: Tue Sep 8 15:41:13 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788846074109 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788846074109 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788845117405 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788846074109 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788845117742 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788846074444 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788845117742 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788846074444 ""}
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 lu " "Found entity 1: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788845126908 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788845126908 ""}
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 lu " "Found entity 1: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788846083748 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788846083748 ""}
|
||||||
{ "Info" "ISGN_START_ELABORATION_TOP" "lu " "Elaborating entity \"lu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788845127047 ""}
|
{ "Info" "ISGN_START_ELABORATION_TOP" "lu " "Elaborating entity \"lu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788846083888 ""}
|
||||||
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788845127799 ""}
|
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788846084609 ""}
|
||||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788845128163 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788845128163 ""}
|
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788846084962 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788846084962 ""}
|
||||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788845128210 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788845128210 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788845128210 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788845128210 ""}
|
{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788846085010 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788846085010 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788846085010 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788846085010 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "439 " "Peak virtual memory: 439 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788845128218 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:25:28 2026 " "Processing ended: Tue Sep 8 15:25:28 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788845128218 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788845128218 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788845128218 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788845128218 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "439 " "Peak virtual memory: 439 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788846085017 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:41:25 2026 " "Processing ended: Tue Sep 8 15:41:25 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788846085017 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788846085017 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788846085017 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788846085017 ""}
|
||||||
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|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788845165953 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788846123810 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788845165953 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:26:05 2026 " "Processing started: Tue Sep 8 15:26:05 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788845165953 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788845165953 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788846123811 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:42:03 2026 " "Processing started: Tue Sep 8 15:42:03 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788846123811 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788846123811 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q2 -c lu " "Command: quartus_sta A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788845165953 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q2 -c lu " "Command: quartus_sta A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788846123811 ""}
|
||||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788845166015 ""}
|
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788846123898 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788845166494 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788846124685 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788845166494 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788846124686 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788845166565 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788846124781 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788845166565 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788846124781 ""}
|
||||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lu.sdc " "Synopsys Design Constraints File file not found: 'lu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788845167169 ""}
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lu.sdc " "Synopsys Design Constraints File file not found: 'lu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788846125575 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788845167170 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788846125575 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788845167170 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788846125576 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788845167171 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788846125576 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788845167171 ""}
|
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788846125577 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788845167171 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788846125577 ""}
|
||||||
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788845167173 ""}
|
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788846125578 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788845167179 ""}
|
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788846125584 ""}
|
||||||
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788845167180 ""}
|
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788846125584 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845167181 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846125585 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845167185 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846125589 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845167186 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846125590 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845167187 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846125591 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845167188 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846125592 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845167188 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846125593 ""}
|
||||||
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788845167191 ""}
|
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788846125596 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788845167229 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788846125648 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788845168178 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788846126673 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788845168268 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788846126766 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788845168268 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788846126766 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788845168268 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788846126766 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788845168268 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788846126767 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845168269 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846126767 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845168271 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846126769 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845168272 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846126770 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845168274 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846126771 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845168275 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846126771 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845168276 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846126772 ""}
|
||||||
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788845168279 ""}
|
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788846126773 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788845168532 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788846127036 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788845169075 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788846127620 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788845169119 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788846127689 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788845169119 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788846127690 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788845169119 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788846127690 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788845169119 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788846127690 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169120 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127692 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169121 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127692 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169122 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127693 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169123 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127694 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169124 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127694 ""}
|
||||||
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788845169125 ""}
|
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788846127696 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788845169274 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788846127873 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788845169274 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788846127873 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788845169275 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788846127874 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788845169275 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788846127874 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169276 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127875 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169277 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127878 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169280 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127880 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169281 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127881 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169282 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127883 ""}
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788845170752 ""}
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788846129404 ""}
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788845170752 ""}
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788846129405 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "738 " "Peak virtual memory: 738 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788845170776 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:26:10 2026 " "Processing ended: Tue Sep 8 15:26:10 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788845170776 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788845170776 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788845170776 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788845170776 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "756 " "Peak virtual memory: 756 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788846129429 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:42:09 2026 " "Processing ended: Tue Sep 8 15:42:09 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788846129429 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788846129429 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788846129429 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788846129429 ""}
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,7 +1,7 @@
|
|||||||
start_full_compilation:s:00:00:57
|
start_full_compilation:s:00:00:59
|
||||||
start_analysis_synthesis:s:00:00:12-start_full_compilation
|
start_analysis_synthesis:s:00:00:12-start_full_compilation
|
||||||
start_analysis_elaboration:s-start_full_compilation
|
start_analysis_elaboration:s-start_full_compilation
|
||||||
start_fitter:s:00:00:30-start_full_compilation
|
start_fitter:s:00:00:30-start_full_compilation
|
||||||
start_assembler:s:00:00:07-start_full_compilation
|
start_assembler:s:00:00:07-start_full_compilation
|
||||||
start_timing_analyzer:s:00:00:06-start_full_compilation
|
start_timing_analyzer:s:00:00:08-start_full_compilation
|
||||||
start_eda_netlist_writer:s:00:00:02-start_full_compilation
|
start_eda_netlist_writer:s:00:00:02-start_full_compilation
|
||||||
@@ -1,136 +1,136 @@
|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788844777337 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788845117404 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788844777337 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:19:37 2026 " "Processing started: Tue Sep 8 15:19:37 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788844777337 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788844777337 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788845117404 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:25:17 2026 " "Processing started: Tue Sep 8 15:25:17 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788845117404 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788845117404 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788844777337 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788845117405 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788844777642 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788845117742 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788844777643 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788845117742 ""}
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 lu " "Found entity 1: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788844787158 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788844787158 ""}
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 lu " "Found entity 1: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788845126908 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788845126908 ""}
|
||||||
{ "Info" "ISGN_START_ELABORATION_TOP" "lu " "Elaborating entity \"lu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788844787299 ""}
|
{ "Info" "ISGN_START_ELABORATION_TOP" "lu " "Elaborating entity \"lu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788845127047 ""}
|
||||||
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788844788196 ""}
|
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788845127799 ""}
|
||||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788844788611 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788844788611 ""}
|
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788845128163 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788845128163 ""}
|
||||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788844788738 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788844788738 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788844788738 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788844788738 ""}
|
{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788845128210 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788845128210 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788845128210 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788845128210 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788844788744 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:19:48 2026 " "Processing ended: Tue Sep 8 15:19:48 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788844788744 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788844788744 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788844788744 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788844788744 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "439 " "Peak virtual memory: 439 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788845128218 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:25:28 2026 " "Processing ended: Tue Sep 8 15:25:28 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788845128218 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788845128218 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788845128218 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788845128218 ""}
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1788844790494 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1788845129672 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788844790495 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:19:49 2026 " "Processing started: Tue Sep 8 15:19:49 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788844790495 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1788844790495 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788845129672 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:25:29 2026 " "Processing started: Tue Sep 8 15:25:29 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788845129672 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1788845129672 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off A1_Q2 -c lu " "Command: quartus_fit --read_settings_files=off --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1788844790495 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off A1_Q2 -c lu " "Command: quartus_fit --read_settings_files=off --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1788845129672 ""}
|
||||||
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1788844790779 ""}
|
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1788845129726 ""}
|
||||||
{ "Info" "0" "" "Project = A1_Q2" { } { } 0 0 "Project = A1_Q2" 0 0 "Fitter" 0 0 1788844790780 ""}
|
{ "Info" "0" "" "Project = A1_Q2" { } { } 0 0 "Project = A1_Q2" 0 0 "Fitter" 0 0 1788845129727 ""}
|
||||||
{ "Info" "0" "" "Revision = lu" { } { } 0 0 "Revision = lu" 0 0 "Fitter" 0 0 1788844790781 ""}
|
{ "Info" "0" "" "Revision = lu" { } { } 0 0 "Revision = lu" 0 0 "Fitter" 0 0 1788845129727 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788844790987 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788845129924 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788844790987 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788845129924 ""}
|
||||||
{ "Info" "IMPP_MPP_USER_DEVICE" "lu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"lu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788844790993 ""}
|
{ "Info" "IMPP_MPP_USER_DEVICE" "lu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"lu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788845129929 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788844791067 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788845130010 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788844791068 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788845130010 ""}
|
||||||
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788844791497 ""}
|
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788845130446 ""}
|
||||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788844791544 ""}
|
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788845130477 ""}
|
||||||
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788844791697 ""}
|
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788845130532 ""}
|
||||||
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "14 14 " "No exact pin location assignment(s) for 14 pins of 14 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1788844791969 ""}
|
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788845137531 ""}
|
||||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788844798727 ""}
|
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788845137551 ""}
|
||||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788844798805 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788845137553 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788844798823 ""}
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788845137553 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788844798823 ""}
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788845137553 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788844798824 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788845137553 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788844798824 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788845137554 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788844798824 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788845137554 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788844798824 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788845137554 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788844798824 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788845137554 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788845137554 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788844798825 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788844798825 ""}
|
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788845137574 ""}
|
||||||
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788844798840 ""}
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lu.sdc " "Synopsys Design Constraints File file not found: 'lu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788845143638 ""}
|
||||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lu.sdc " "Synopsys Design Constraints File file not found: 'lu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788844804981 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788845143639 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788844804982 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788845143639 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788844804982 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788845143640 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788844804983 ""}
|
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788845143640 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788844804985 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788845143641 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788844804985 ""}
|
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788845143641 ""}
|
||||||
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788844804985 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788845143644 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788844804990 ""}
|
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788845143727 ""}
|
||||||
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788844805033 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788845144437 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788844806561 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788845145074 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788844807646 ""}
|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788845145346 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788844808016 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788845145346 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788844808016 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788845145947 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788844808589 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788845151771 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788845151771 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X57_Y24 X68_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y24 to location X68_Y36" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y24 to location X68_Y36"} { { 12 { 0 ""} 57 24 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788844814262 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788844814262 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788845152005 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788845152005 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788845152005 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788844814418 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788844814418 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788844814418 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788845152008 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788844814421 ""}
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788845153127 ""}
|
||||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.10 " "Total time spent on timing analysis during the Fitter is 0.10 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788844815480 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788845153162 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788844815517 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788845153534 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788844815904 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788845153534 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788844815904 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788845154081 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788844816449 ""}
|
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788845156793 ""}
|
||||||
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788844819073 ""}
|
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1788845157057 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1341 " "Peak virtual memory: 1341 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788844819911 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:20:19 2026 " "Processing ended: Tue Sep 8 15:20:19 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788844819911 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788844819911 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:42 " "Total CPU time (on all processors): 00:00:42" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788844819911 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788844819911 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1342 " "Peak virtual memory: 1342 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788845157620 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:25:57 2026 " "Processing ended: Tue Sep 8 15:25:57 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788845157620 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788845157620 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:40 " "Total CPU time (on all processors): 00:00:40" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788845157620 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788845157620 ""}
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1788844821731 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1788845159220 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788844821731 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:20:21 2026 " "Processing started: Tue Sep 8 15:20:21 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788844821731 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788844821731 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788845159221 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:25:59 2026 " "Processing started: Tue Sep 8 15:25:59 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788845159221 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788845159221 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q2 -c lu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788844821732 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q2 -c lu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788845159221 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788844822417 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788845159892 ""}
|
||||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788844827122 ""}
|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788845164360 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "521 " "Peak virtual memory: 521 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788844827324 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:20:27 2026 " "Processing ended: Tue Sep 8 15:20:27 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788844827324 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788844827324 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788844827324 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788844827324 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "513 " "Peak virtual memory: 513 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788845164529 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:26:04 2026 " "Processing ended: Tue Sep 8 15:26:04 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788845164529 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788845164529 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788845164529 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788845164529 ""}
|
||||||
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1788844828123 ""}
|
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1788845165209 ""}
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1788844828885 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1788845165953 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788844828886 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:20:28 2026 " "Processing started: Tue Sep 8 15:20:28 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788844828886 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788844828886 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788845165953 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:26:05 2026 " "Processing started: Tue Sep 8 15:26:05 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788845165953 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788845165953 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q2 -c lu " "Command: quartus_sta A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788844828886 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q2 -c lu " "Command: quartus_sta A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788845165953 ""}
|
||||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788844828964 ""}
|
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788845166015 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788844829446 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788845166494 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788844829446 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788845166494 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788844829519 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788845166565 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788844829519 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788845166565 ""}
|
||||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lu.sdc " "Synopsys Design Constraints File file not found: 'lu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788844830103 ""}
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lu.sdc " "Synopsys Design Constraints File file not found: 'lu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788845167169 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788844830103 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788845167170 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788844830104 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788845167170 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788844830104 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788845167171 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788844830104 ""}
|
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788845167171 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788844830105 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788845167171 ""}
|
||||||
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788844830105 ""}
|
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788845167173 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788844830109 ""}
|
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788845167179 ""}
|
||||||
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788844830110 ""}
|
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788845167180 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844830111 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845167181 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844830123 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845167185 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844830124 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845167186 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844830125 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845167187 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844830126 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845167188 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844830126 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845167188 ""}
|
||||||
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788844830128 ""}
|
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788845167191 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788844830170 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788845167229 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788844831123 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788845168178 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788844831219 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788845168268 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788844831219 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788845168268 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788844831219 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788845168268 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788844831220 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788845168268 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844831220 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845168269 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844831222 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845168271 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844831223 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845168272 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844831224 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845168274 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844831224 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845168275 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844831225 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845168276 ""}
|
||||||
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788844831227 ""}
|
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788845168279 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788844831482 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788845168532 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788844832022 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788845169075 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788844832064 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788845169119 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788844832064 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788845169119 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788844832064 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788845169119 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788844832064 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788845169119 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844832065 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169120 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844832066 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169121 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844832067 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169122 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844832068 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169123 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844832068 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169124 ""}
|
||||||
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788844832070 ""}
|
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788845169125 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788844832214 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788845169274 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788844832214 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788845169274 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788844832214 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788845169275 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788844832214 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788845169275 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844832215 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169276 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844832216 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169277 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844832217 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169280 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844832217 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169281 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788844832218 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788845169282 ""}
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788844833709 ""}
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788845170752 ""}
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788844833710 ""}
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788845170752 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "757 " "Peak virtual memory: 757 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788844833732 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:20:33 2026 " "Processing ended: Tue Sep 8 15:20:33 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788844833732 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788844833732 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788844833732 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788844833732 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "738 " "Peak virtual memory: 738 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788845170776 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:26:10 2026 " "Processing ended: Tue Sep 8 15:26:10 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788845170776 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788845170776 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788845170776 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788845170776 ""}
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1788844835398 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1788845172313 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788844835399 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:20:35 2026 " "Processing started: Tue Sep 8 15:20:35 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788844835399 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788844835399 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788845172313 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:26:12 2026 " "Processing started: Tue Sep 8 15:26:12 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788845172313 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788845172313 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q2 -c lu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788844835399 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q2 -c lu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788845172314 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788844836147 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788845173068 ""}
|
||||||
{ "Info" "IWSC_DONE_HDL_GENERATION" "lu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/simulation/questa/ simulation " "Generated file lu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788844836215 ""}
|
{ "Info" "IWSC_DONE_HDL_GENERATION" "lu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/simulation/questa/ simulation " "Generated file lu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788845173114 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "670 " "Peak virtual memory: 670 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788844836246 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:20:36 2026 " "Processing ended: Tue Sep 8 15:20:36 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788844836246 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788844836246 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788844836246 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788844836246 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788845173146 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:26:13 2026 " "Processing ended: Tue Sep 8 15:26:13 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788845173146 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788845173146 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788845173146 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788845173146 ""}
|
||||||
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 15 s " "Quartus Prime Full Compilation was successful. 0 errors, 15 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788844836918 ""}
|
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 15 s " "Quartus Prime Full Compilation was successful. 0 errors, 15 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788845173822 ""}
|
||||||
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@@ -1,5 +1,5 @@
|
|||||||
Assembler report for lu
|
Assembler report for lu
|
||||||
Tue Sep 8 15:26:04 2026
|
Tue Sep 8 15:42:01 2026
|
||||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
|
|
||||||
|
|
||||||
@@ -38,7 +38,7 @@ on the Quartus Prime software download page.
|
|||||||
+---------------------------------------------------------------+
|
+---------------------------------------------------------------+
|
||||||
; Assembler Summary ;
|
; Assembler Summary ;
|
||||||
+-----------------------+---------------------------------------+
|
+-----------------------+---------------------------------------+
|
||||||
; Assembler Status ; Successful - Tue Sep 8 15:26:04 2026 ;
|
; Assembler Status ; Successful - Tue Sep 8 15:42:01 2026 ;
|
||||||
; Revision Name ; lu ;
|
; Revision Name ; lu ;
|
||||||
; Top-level Entity Name ; lu ;
|
; Top-level Entity Name ; lu ;
|
||||||
; Family ; Cyclone V ;
|
; Family ; Cyclone V ;
|
||||||
@@ -78,14 +78,14 @@ on the Quartus Prime software download page.
|
|||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus Prime Assembler
|
Info: Running Quartus Prime Assembler
|
||||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
Info: Processing started: Tue Sep 8 15:25:59 2026
|
Info: Processing started: Tue Sep 8 15:41:55 2026
|
||||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q2 -c lu
|
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q2 -c lu
|
||||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
Info (115030): Assembler is generating device programming files
|
Info (115030): Assembler is generating device programming files
|
||||||
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
|
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
|
||||||
Info: Peak virtual memory: 513 megabytes
|
Info: Peak virtual memory: 513 megabytes
|
||||||
Info: Processing ended: Tue Sep 8 15:26:04 2026
|
Info: Processing ended: Tue Sep 8 15:42:01 2026
|
||||||
Info: Elapsed time: 00:00:05
|
Info: Elapsed time: 00:00:06
|
||||||
Info: Total CPU time (on all processors): 00:00:05
|
Info: Total CPU time (on all processors): 00:00:06
|
||||||
|
|
||||||
|
|
||||||
@@ -1 +1 @@
|
|||||||
Tue Sep 8 15:26:13 2026
|
Tue Sep 8 15:42:12 2026
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
EDA Netlist Writer report for lu
|
EDA Netlist Writer report for lu
|
||||||
Tue Sep 8 15:26:13 2026
|
Tue Sep 8 15:42:11 2026
|
||||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
|
|
||||||
|
|
||||||
@@ -37,7 +37,7 @@ on the Quartus Prime software download page.
|
|||||||
+-------------------------------------------------------------------+
|
+-------------------------------------------------------------------+
|
||||||
; EDA Netlist Writer Summary ;
|
; EDA Netlist Writer Summary ;
|
||||||
+---------------------------+---------------------------------------+
|
+---------------------------+---------------------------------------+
|
||||||
; EDA Netlist Writer Status ; Successful - Tue Sep 8 15:26:13 2026 ;
|
; EDA Netlist Writer Status ; Successful - Tue Sep 8 15:42:11 2026 ;
|
||||||
; Revision Name ; lu ;
|
; Revision Name ; lu ;
|
||||||
; Top-level Entity Name ; lu ;
|
; Top-level Entity Name ; lu ;
|
||||||
; Family ; Cyclone V ;
|
; Family ; Cyclone V ;
|
||||||
@@ -81,13 +81,13 @@ on the Quartus Prime software download page.
|
|||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus Prime EDA Netlist Writer
|
Info: Running Quartus Prime EDA Netlist Writer
|
||||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
Info: Processing started: Tue Sep 8 15:26:12 2026
|
Info: Processing started: Tue Sep 8 15:42:10 2026
|
||||||
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q2 -c lu
|
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q2 -c lu
|
||||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
Info (204019): Generated file lu.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/simulation/questa/" for EDA simulation tool
|
Info (204019): Generated file lu.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/simulation/questa/" for EDA simulation tool
|
||||||
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
|
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
|
||||||
Info: Peak virtual memory: 658 megabytes
|
Info: Peak virtual memory: 658 megabytes
|
||||||
Info: Processing ended: Tue Sep 8 15:26:13 2026
|
Info: Processing ended: Tue Sep 8 15:42:11 2026
|
||||||
Info: Elapsed time: 00:00:01
|
Info: Elapsed time: 00:00:01
|
||||||
Info: Total CPU time (on all processors): 00:00:01
|
Info: Total CPU time (on all processors): 00:00:01
|
||||||
|
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
Fitter report for lu
|
Fitter report for lu
|
||||||
Tue Sep 8 15:25:57 2026
|
Tue Sep 8 15:41:53 2026
|
||||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
|
|
||||||
|
|
||||||
@@ -58,7 +58,7 @@ on the Quartus Prime software download page.
|
|||||||
+-----------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------+
|
||||||
; Fitter Summary ;
|
; Fitter Summary ;
|
||||||
+---------------------------------+-------------------------------------------------+
|
+---------------------------------+-------------------------------------------------+
|
||||||
; Fitter Status ; Successful - Tue Sep 8 15:25:57 2026 ;
|
; Fitter Status ; Successful - Tue Sep 8 15:41:53 2026 ;
|
||||||
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
||||||
; Revision Name ; lu ;
|
; Revision Name ; lu ;
|
||||||
; Top-level Entity Name ; lu ;
|
; Top-level Entity Name ; lu ;
|
||||||
@@ -1371,11 +1371,11 @@ Info (334003): Started post-fitting delay annotation
|
|||||||
Info (334004): Delay annotation completed successfully
|
Info (334004): Delay annotation completed successfully
|
||||||
Info (334003): Started post-fitting delay annotation
|
Info (334003): Started post-fitting delay annotation
|
||||||
Info (334004): Delay annotation completed successfully
|
Info (334004): Delay annotation completed successfully
|
||||||
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
|
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
|
||||||
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
|
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
|
||||||
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
|
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
|
||||||
Info: Peak virtual memory: 1342 megabytes
|
Info: Peak virtual memory: 1336 megabytes
|
||||||
Info: Processing ended: Tue Sep 8 15:25:57 2026
|
Info: Processing ended: Tue Sep 8 15:41:54 2026
|
||||||
Info: Elapsed time: 00:00:28
|
Info: Elapsed time: 00:00:28
|
||||||
Info: Total CPU time (on all processors): 00:00:40
|
Info: Total CPU time (on all processors): 00:00:40
|
||||||
|
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
Fitter Status : Successful - Tue Sep 8 15:25:57 2026
|
Fitter Status : Successful - Tue Sep 8 15:41:53 2026
|
||||||
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
Revision Name : lu
|
Revision Name : lu
|
||||||
Top-level Entity Name : lu
|
Top-level Entity Name : lu
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
Flow report for lu
|
Flow report for lu
|
||||||
Tue Sep 8 15:26:13 2026
|
Tue Sep 8 15:42:11 2026
|
||||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
|
|
||||||
|
|
||||||
@@ -41,7 +41,7 @@ on the Quartus Prime software download page.
|
|||||||
+-----------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------+
|
||||||
; Flow Summary ;
|
; Flow Summary ;
|
||||||
+---------------------------------+-------------------------------------------------+
|
+---------------------------------+-------------------------------------------------+
|
||||||
; Flow Status ; Successful - Tue Sep 8 15:26:13 2026 ;
|
; Flow Status ; Successful - Tue Sep 8 15:42:11 2026 ;
|
||||||
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
||||||
; Revision Name ; lu ;
|
; Revision Name ; lu ;
|
||||||
; Top-level Entity Name ; lu ;
|
; Top-level Entity Name ; lu ;
|
||||||
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
|
|||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
; Option ; Setting ;
|
; Option ; Setting ;
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
; Start date & time ; 09/08/2026 15:25:17 ;
|
; Start date & time ; 09/08/2026 15:41:14 ;
|
||||||
; Main task ; Compilation ;
|
; Main task ; Compilation ;
|
||||||
; Revision Name ; lu ;
|
; Revision Name ; lu ;
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
|
|||||||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||||
; COMPILER_SIGNATURE_ID ; 86000517901476.178884511706024 ; -- ; -- ; -- ;
|
; COMPILER_SIGNATURE_ID ; 86000517901476.178884607407150 ; -- ; -- ; -- ;
|
||||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
|
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
|
||||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
|
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
|
||||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
|
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
|
||||||
@@ -102,11 +102,11 @@ on the Quartus Prime software download page.
|
|||||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 422 MB ; 00:00:25 ;
|
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 422 MB ; 00:00:25 ;
|
||||||
; Fitter ; 00:00:28 ; 1.0 ; 1342 MB ; 00:00:39 ;
|
; Fitter ; 00:00:27 ; 1.0 ; 1336 MB ; 00:00:40 ;
|
||||||
; Assembler ; 00:00:05 ; 1.0 ; 513 MB ; 00:00:05 ;
|
; Assembler ; 00:00:06 ; 1.0 ; 513 MB ; 00:00:06 ;
|
||||||
; Timing Analyzer ; 00:00:05 ; 1.0 ; 738 MB ; 00:00:05 ;
|
; Timing Analyzer ; 00:00:06 ; 1.0 ; 756 MB ; 00:00:06 ;
|
||||||
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ;
|
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ;
|
||||||
; Total ; 00:00:50 ; -- ; -- ; 00:01:15 ;
|
; Total ; 00:00:51 ; -- ; -- ; 00:01:18 ;
|
||||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
Analysis & Synthesis report for lu
|
Analysis & Synthesis report for lu
|
||||||
Tue Sep 8 15:25:28 2026
|
Tue Sep 8 15:41:25 2026
|
||||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
|
|
||||||
|
|
||||||
@@ -45,7 +45,7 @@ on the Quartus Prime software download page.
|
|||||||
+-----------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------+
|
||||||
; Analysis & Synthesis Summary ;
|
; Analysis & Synthesis Summary ;
|
||||||
+---------------------------------+-------------------------------------------------+
|
+---------------------------------+-------------------------------------------------+
|
||||||
; Analysis & Synthesis Status ; Successful - Tue Sep 8 15:25:28 2026 ;
|
; Analysis & Synthesis Status ; Successful - Tue Sep 8 15:41:25 2026 ;
|
||||||
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
||||||
; Revision Name ; lu ;
|
; Revision Name ; lu ;
|
||||||
; Top-level Entity Name ; lu ;
|
; Top-level Entity Name ; lu ;
|
||||||
@@ -278,7 +278,7 @@ Note: In order to hide this table in the UI and the text report file, please set
|
|||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus Prime Analysis & Synthesis
|
Info: Running Quartus Prime Analysis & Synthesis
|
||||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
Info: Processing started: Tue Sep 8 15:25:17 2026
|
Info: Processing started: Tue Sep 8 15:41:13 2026
|
||||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu
|
||||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
||||||
@@ -294,8 +294,8 @@ Info (21057): Implemented 18 device resources after synthesis - the final resour
|
|||||||
Info (21061): Implemented 4 logic cells
|
Info (21061): Implemented 4 logic cells
|
||||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
|
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
|
||||||
Info: Peak virtual memory: 439 megabytes
|
Info: Peak virtual memory: 439 megabytes
|
||||||
Info: Processing ended: Tue Sep 8 15:25:28 2026
|
Info: Processing ended: Tue Sep 8 15:41:25 2026
|
||||||
Info: Elapsed time: 00:00:11
|
Info: Elapsed time: 00:00:12
|
||||||
Info: Total CPU time (on all processors): 00:00:25
|
Info: Total CPU time (on all processors): 00:00:25
|
||||||
|
|
||||||
|
|
||||||
@@ -1,4 +1,4 @@
|
|||||||
Analysis & Synthesis Status : Successful - Tue Sep 8 15:25:28 2026
|
Analysis & Synthesis Status : Successful - Tue Sep 8 15:41:25 2026
|
||||||
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
Revision Name : lu
|
Revision Name : lu
|
||||||
Top-level Entity Name : lu
|
Top-level Entity Name : lu
|
||||||
|
|||||||
Binary file not shown.
@@ -1,5 +1,5 @@
|
|||||||
Timing Analyzer report for lu
|
Timing Analyzer report for lu
|
||||||
Tue Sep 8 15:26:10 2026
|
Tue Sep 8 15:42:09 2026
|
||||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
|
|
||||||
|
|
||||||
@@ -461,7 +461,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus Prime Timing Analyzer
|
Info: Running Quartus Prime Timing Analyzer
|
||||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
Info: Processing started: Tue Sep 8 15:26:05 2026
|
Info: Processing started: Tue Sep 8 15:42:03 2026
|
||||||
Info: Command: quartus_sta A1_Q2 -c lu
|
Info: Command: quartus_sta A1_Q2 -c lu
|
||||||
Info: qsta_default_script.tcl version: #1
|
Info: qsta_default_script.tcl version: #1
|
||||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
@@ -521,9 +521,9 @@ Info (332140): No Minimum Pulse Width paths to report
|
|||||||
Info (332102): Design is not fully constrained for setup requirements
|
Info (332102): Design is not fully constrained for setup requirements
|
||||||
Info (332102): Design is not fully constrained for hold requirements
|
Info (332102): Design is not fully constrained for hold requirements
|
||||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
|
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
|
||||||
Info: Peak virtual memory: 738 megabytes
|
Info: Peak virtual memory: 756 megabytes
|
||||||
Info: Processing ended: Tue Sep 8 15:26:10 2026
|
Info: Processing ended: Tue Sep 8 15:42:09 2026
|
||||||
Info: Elapsed time: 00:00:05
|
Info: Elapsed time: 00:00:06
|
||||||
Info: Total CPU time (on all processors): 00:00:05
|
Info: Total CPU time (on all processors): 00:00:06
|
||||||
|
|
||||||
|
|
||||||
@@ -17,7 +17,7 @@
|
|||||||
// PROGRAM "Quartus Prime"
|
// PROGRAM "Quartus Prime"
|
||||||
// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
|
// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
|
||||||
|
|
||||||
// DATE "09/08/2026 15:26:13"
|
// DATE "09/08/2026 15:42:11"
|
||||||
|
|
||||||
//
|
//
|
||||||
// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
|
// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
|
||||||
@@ -34,10 +34,10 @@ module lu (
|
|||||||
A,
|
A,
|
||||||
B,
|
B,
|
||||||
Y);
|
Y);
|
||||||
input [1:0] op;
|
input logic [1:0] op ;
|
||||||
input [3:0] A;
|
input logic [3:0] A ;
|
||||||
input [3:0] B;
|
input logic [3:0] B ;
|
||||||
output [3:0] Y;
|
output logic [3:0] Y ;
|
||||||
|
|
||||||
// Design Ports Information
|
// Design Ports Information
|
||||||
// Y[0] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default
|
// Y[0] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default
|
||||||
|
|||||||
Binary file not shown.
@@ -1,3 +1,3 @@
|
|||||||
Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
Version_Index = 604268800
|
Version_Index = 604268800
|
||||||
Creation_Time = Fri Sep 4 13:02:46 2026
|
Creation_Time = Tue Sep 8 15:43:22 2026
|
||||||
+5
-4
@@ -1,8 +1,9 @@
|
|||||||
module asu #(width=8)(input logic [0:0] op,
|
module asu #(parameter width = 2)(
|
||||||
input logic[width-1:0] A, input logic[width-1:0] B,
|
input logic [0:0] op,
|
||||||
output logic[width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
|
input logic[2**width-1:0] A, input logic[2**width-1:0] B,
|
||||||
|
output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
|
||||||
|
|
||||||
logic [width-1:0] operand;
|
logic [2**width-1:0] operand;
|
||||||
always_comb begin
|
always_comb begin
|
||||||
// A + (sub) ? B : -B
|
// A + (sub) ? B : -B
|
||||||
// Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
|
// Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
|
||||||
|
|||||||
@@ -0,0 +1,16 @@
|
|||||||
|
module asu #(width=8)(input logic [0:0] op,
|
||||||
|
input logic[width-1:0] A, input logic[width-1:0] B,
|
||||||
|
output logic[width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
|
||||||
|
|
||||||
|
logic [width-1:0] operand;
|
||||||
|
always_comb begin
|
||||||
|
// A + (sub) ? B : -B
|
||||||
|
// Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
|
||||||
|
operand = (B ^ {(width){op}});
|
||||||
|
{COUT, OUT_1} = A + operand + {{(width-1){1'b0}}, op};
|
||||||
|
end
|
||||||
|
|
||||||
|
// Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
|
||||||
|
// Cin for width-2'th bit to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
|
||||||
|
assign OUT_CIN = A[width-1] ^ operand[width-1] ^ OUT_1[width-1];
|
||||||
|
endmodule
|
||||||
+3
-3
@@ -1,13 +1,13 @@
|
|||||||
`include "lu.sv"
|
`include "lu.sv"
|
||||||
|
|
||||||
module lu_tb #(W=8)();
|
module lu_tb #(parameter W=4)();
|
||||||
logic [1:0] op;
|
logic [1:0] op;
|
||||||
logic [W-1:0] A;
|
logic [W-1:0] A;
|
||||||
logic [W-1:0] B;
|
logic [W-1:0] B;
|
||||||
logic [W-1:0] C;
|
logic [W-1:0] C;
|
||||||
logic [W-1:0] C_exp[16];
|
logic [W-1:0] C_exp[16];
|
||||||
|
|
||||||
lu #(W) dut();
|
lu #(W/2) dut();
|
||||||
|
|
||||||
integer error_count;
|
integer error_count;
|
||||||
initial begin
|
initial begin
|
||||||
@@ -56,4 +56,4 @@ module lu_tb #(W=8)();
|
|||||||
if (error_count == 0) $display("\x1b[38;5;10mAll LU tests passing\x1b[m");
|
if (error_count == 0) $display("\x1b[38;5;10mAll LU tests passing\x1b[m");
|
||||||
else $display("\x1b[38;5;9m%0d LU test(s) failing\x1b[m", error_count);
|
else $display("\x1b[38;5;9m%0d LU test(s) failing\x1b[m", error_count);
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
@@ -0,0 +1,59 @@
|
|||||||
|
`include "lu.sv"
|
||||||
|
|
||||||
|
module lu_tb #(W=4)();
|
||||||
|
logic [1:0] op;
|
||||||
|
logic [W-1:0] A;
|
||||||
|
logic [W-1:0] B;
|
||||||
|
logic [W-1:0] C;
|
||||||
|
logic [W-1:0] C_exp[16];
|
||||||
|
|
||||||
|
lu #(2) dut();
|
||||||
|
|
||||||
|
integer error_count;
|
||||||
|
initial begin
|
||||||
|
// AND
|
||||||
|
C_exp[0] = {W{1'b0}};
|
||||||
|
C_exp[1] = {W{1'b0}};
|
||||||
|
C_exp[2] = {W{1'b0}};
|
||||||
|
C_exp[3] = {W{1'b0}};
|
||||||
|
// OR
|
||||||
|
C_exp[4] = {W{1'b0}};
|
||||||
|
C_exp[5] = {W{1'b1}};
|
||||||
|
C_exp[6] = {W{1'b1}};
|
||||||
|
C_exp[7] = {W{1'b1}};
|
||||||
|
// XOR
|
||||||
|
C_exp[8] = {W{1'b0}};
|
||||||
|
C_exp[9] = {W{1'b1}};
|
||||||
|
C_exp[10] = {W{1'b1}};
|
||||||
|
C_exp[11] = {W{1'b0}};
|
||||||
|
// NOR
|
||||||
|
C_exp[12] = {W{1'b1}};
|
||||||
|
C_exp[13] = {W{1'b0}};
|
||||||
|
C_exp[14] = {W{1'b0}};
|
||||||
|
C_exp[15] = {W{1'b0}};
|
||||||
|
|
||||||
|
error_count = 0;
|
||||||
|
op = 0;
|
||||||
|
A = 0;
|
||||||
|
B = 0;
|
||||||
|
$display("Beginning LU tests");
|
||||||
|
for (integer N = 0; N < 4; ++N) begin
|
||||||
|
for (integer M = 0; M < 2; ++M) begin
|
||||||
|
for (integer K = 0; K < 2; ++K) begin
|
||||||
|
#1;
|
||||||
|
if (C != C_exp[N*2*2 + M*2 + K]) begin
|
||||||
|
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", op, A, B, C, C_exp[N*2*2 + M*2 + K]);
|
||||||
|
error_count = error_count + 1;
|
||||||
|
end
|
||||||
|
B = 1;
|
||||||
|
end
|
||||||
|
A = 1;
|
||||||
|
end
|
||||||
|
A = 0;
|
||||||
|
B = 0;
|
||||||
|
op = op + 1;
|
||||||
|
end
|
||||||
|
if (error_count == 0) $display("\x1b[38;5;10mAll LU tests passing\x1b[m");
|
||||||
|
else $display("\x1b[38;5;9m%0d LU test(s) failing\x1b[m", error_count);
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
Reference in new issue
Block a user