Added ModelSim folder (and have to add files into it as to allow for different testbench code)

modules/asu.sv

@@ -1,8 +1,9 @@
-module asu #(width=8)(input logic [0:0] op,
-    input logic[width-1:0] A, input logic[width-1:0] B,
-    output logic[width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
+module asu #(parameter width = 2)(
+	input logic [0:0] op,
+	input logic[2**width-1:0] A, input logic[2**width-1:0] B,
+   output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
 
-    logic [width-1:0] operand;
+    logic [2**width-1:0] operand;
     always_comb begin
         // A + (sub) ? B : -B
         // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis