Added ModelSim folder (and have to add files into it as to allow for different testbench code)

Quartus/A1_Q2/simulation/questa/lu.svo

@@ -17,7 +17,7 @@
 // PROGRAM "Quartus Prime"
 // VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
 
-// DATE "09/08/2026 15:26:13"
+// DATE "09/08/2026 15:42:11"
 
 // 
 // Device: Altera 5CGXFC5C6F27C7 Package FBGA672
@@ -34,10 +34,10 @@ module lu (
 	A,
 	B,
 	Y);
-input 	[1:0] op;
-input 	[3:0] A;
-input 	[3:0] B;
-output 	[3:0] Y;
+input 	logic [1:0] op ;
+input 	logic [3:0] A ;
+input 	logic [3:0] B ;
+output 	logic [3:0] Y ;
 
 // Design Ports Information
 // Y[0]	=>  Location: PIN_F7,	 I/O Standard: 2.5 V,	 Current Strength: Default