Added ModelSim folder (and have to add files into it as to allow for different testbench code)

Quartus/A1_Q2/output_files/lu.sta.rpt

@@ -1,5 +1,5 @@
 Timing Analyzer report for lu
-Tue Sep  8 15:26:10 2026
+Tue Sep  8 15:42:09 2026
 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 
 
@@ -461,7 +461,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 Info: *******************************************************************
 Info: Running Quartus Prime Timing Analyzer
     Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-    Info: Processing started: Tue Sep  8 15:26:05 2026
+    Info: Processing started: Tue Sep  8 15:42:03 2026
 Info: Command: quartus_sta A1_Q2 -c lu
 Info: qsta_default_script.tcl version: #1
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@@ -521,9 +521,9 @@ Info (332140): No Minimum Pulse Width paths to report
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
 Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
-    Info: Peak virtual memory: 738 megabytes
-    Info: Processing ended: Tue Sep  8 15:26:10 2026
-    Info: Elapsed time: 00:00:05
-    Info: Total CPU time (on all processors): 00:00:05
+    Info: Peak virtual memory: 756 megabytes
+    Info: Processing ended: Tue Sep  8 15:42:09 2026
+    Info: Elapsed time: 00:00:06
+    Info: Total CPU time (on all processors): 00:00:06