TroubleElectrical/FPGA_Uni
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Added ModelSim folder (and have to add files into it as to allow for different testbench code)

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TroubleElectrical committed 2026-09-08 16:32:01 +10:00
1 parent 2208eb4f16
commit 60e5dae43b
72 files changed
+1049 -320
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Quartus/A1_Q2/db/lu.tmw_info
+2 -2
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@@ -1,7 +1,7 @@
start_full_compilation:s:00:00:57
start_full_compilation:s:00:00:59
start_analysis_synthesis:s:00:00:12-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:30-start_full_compilation
start_assembler:s:00:00:07-start_full_compilation
start_timing_analyzer:s:00:00:06-start_full_compilation
start_timing_analyzer:s:00:00:08-start_full_compilation
start_eda_netlist_writer:s:00:00:02-start_full_compilation