TroubleElectrical/FPGA_Uni
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Added ModelSim folder (and have to add files into it as to allow for different testbench code)

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TroubleElectrical committed 2026-09-08 16:32:01 +10:00
1 parent 2208eb4f16
commit 60e5dae43b
72 files changed
+1049 -320
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Quartus/A1_Q2/db/lu.hier_info
+4 -4
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@@ -31,9 +31,9 @@ B[2] => Y.IN1
B[3] => Y.IN1
B[3] => Y.IN1
B[3] => Y.IN1
Y[0] << Mux3.DB_MAX_OUTPUT_PORT_TYPE
Y[1] << Mux2.DB_MAX_OUTPUT_PORT_TYPE
Y[2] << Mux1.DB_MAX_OUTPUT_PORT_TYPE
Y[3] << Mux0.DB_MAX_OUTPUT_PORT_TYPE
Y[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
Y[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
Y[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
Y[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE