Added ModelSim folder (and have to add files into it as to allow for different testbench code)

ModelSim/transcript

@@ -0,0 +1,46 @@
+# Loading project Assignment_1_Q2
+# Compile of lu.sv was successful.
+# Compile of lu_tb.sv failed with 1 errors.
+# 2 compiles, 1 failed with 1 error.
+# Compile of lu_tb.sv failed with 1 errors.
+# Compile of lu.sv was successful.
+# Compile of lu_tb.sv was successful.
+# 2 compiles, 0 failed with no errors.
+vsim work.lu_tb
+# vsim work.lu_tb 
+# Start time: 16:26:37 on Sep 08,2026
+# Loading sv_std.std
+# Loading work.lu_tb
+# Loading work.lu
+# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'dut'.  Expected 4, found 0.
+#    Time: 0 ps  Iteration: 0  Instance: /lu_tb/dut File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv Line: 10
+# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'op'.
+# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'A'.
+# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'B'.
+# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'Y'.
+add wave -position end  sim:/lu_tb/op
+add wave -position end  sim:/lu_tb/A
+add wave -position end  sim:/lu_tb/A
+add wave -position end  sim:/lu_tb/B
+add wave -position end  sim:/lu_tb/C
+quit -sim
+# End time: 16:28:07 on Sep 08,2026, Elapsed time: 0:01:30
+# Errors: 0, Warnings: 12
+# Compile of lu.sv was successful.
+# Compile of lu_tb.sv was successful.
+# 2 compiles, 0 failed with no errors.
+vsim work.lu_tb
+# vsim work.lu_tb 
+# Start time: 16:30:51 on Sep 08,2026
+# Loading sv_std.std
+# Loading work.lu_tb
+# Loading work.lu
+# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'dut'.  Expected 4, found 0.
+#    Time: 0 ps  Iteration: 0  Instance: /lu_tb/dut File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv Line: 10
+# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'op'.
+# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'A'.
+# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'B'.
+# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'Y'.
+quit -sim
+# End time: 16:31:17 on Sep 08,2026, Elapsed time: 0:00:26
+# Errors: 0, Warnings: 7