Added 4 digit 7seg display module (confirmed working for now),
Added Inputs for displaying registers / Program Counter high and low bits, Assigned pins for Display digits, inputs (Labeled HID) and the clk button
This commit is contained in:
138 files changed
+2431
-744
No files matched your search
@@ -1,5 +1,5 @@
|
||||
Assembler report for assignment2
|
||||
Tue Oct 13 15:09:01 2026
|
||||
Tue Oct 13 16:19:01 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
@@ -38,7 +38,7 @@ on the Quartus Prime software download page.
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Tue Oct 13 15:09:01 2026 ;
|
||||
; Assembler Status ; Successful - Tue Oct 13 16:19:01 2026 ;
|
||||
; Revision Name ; assignment2 ;
|
||||
; Top-level Entity Name ; assignment2 ;
|
||||
; Family ; Cyclone V ;
|
||||
@@ -67,8 +67,8 @@ on the Quartus Prime software download page.
|
||||
+----------------+--------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+--------------------------+
|
||||
; JTAG usercode ; 0x0077D665 ;
|
||||
; Checksum ; 0x0077D665 ;
|
||||
; JTAG usercode ; 0x00780D54 ;
|
||||
; Checksum ; 0x00780D54 ;
|
||||
+----------------+--------------------------+
|
||||
|
||||
|
||||
@@ -78,14 +78,14 @@ on the Quartus Prime software download page.
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Assembler
|
||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Info: Processing started: Tue Oct 13 15:08:55 2026
|
||||
Info: Processing started: Tue Oct 13 16:18:55 2026
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 521 megabytes
|
||||
Info: Processing ended: Tue Oct 13 15:09:01 2026
|
||||
Info: Peak virtual memory: 508 megabytes
|
||||
Info: Processing ended: Tue Oct 13 16:19:01 2026
|
||||
Info: Elapsed time: 00:00:06
|
||||
Info: Total CPU time (on all processors): 00:00:05
|
||||
Info: Total CPU time (on all processors): 00:00:06
|
||||
|
||||
|
||||
@@ -1 +1 @@
|
||||
Tue Oct 13 15:09:09 2026
|
||||
Tue Oct 13 16:19:11 2026
|
||||
@@ -1,5 +1,5 @@
|
||||
EDA Netlist Writer report for assignment2
|
||||
Tue Oct 13 15:09:08 2026
|
||||
Tue Oct 13 16:19:10 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
@@ -37,7 +37,7 @@ on the Quartus Prime software download page.
|
||||
+-------------------------------------------------------------------+
|
||||
; EDA Netlist Writer Summary ;
|
||||
+---------------------------+---------------------------------------+
|
||||
; EDA Netlist Writer Status ; Successful - Tue Oct 13 15:09:08 2026 ;
|
||||
; EDA Netlist Writer Status ; Successful - Tue Oct 13 16:19:10 2026 ;
|
||||
; Revision Name ; assignment2 ;
|
||||
; Top-level Entity Name ; assignment2 ;
|
||||
; Family ; Cyclone V ;
|
||||
@@ -81,13 +81,13 @@ on the Quartus Prime software download page.
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime EDA Netlist Writer
|
||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Info: Processing started: Tue Oct 13 15:09:07 2026
|
||||
Info: Processing started: Tue Oct 13 16:19:09 2026
|
||||
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (204019): Generated file assignment2.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/" for EDA simulation tool
|
||||
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 659 megabytes
|
||||
Info: Processing ended: Tue Oct 13 15:09:08 2026
|
||||
Info: Peak virtual memory: 670 megabytes
|
||||
Info: Processing ended: Tue Oct 13 16:19:10 2026
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
Fitter report for assignment2
|
||||
Tue Oct 13 15:08:53 2026
|
||||
Tue Oct 13 16:18:53 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
@@ -10,26 +10,28 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
2. Fitter Summary
|
||||
3. Fitter Settings
|
||||
4. Parallel Compilation
|
||||
5. Incremental Compilation Preservation Summary
|
||||
6. Incremental Compilation Partition Settings
|
||||
7. Incremental Compilation Placement Preservation
|
||||
8. Pin-Out File
|
||||
9. Fitter Resource Usage Summary
|
||||
10. Fitter Partition Statistics
|
||||
11. Input Pins
|
||||
12. I/O Bank Usage
|
||||
13. All Package Pins
|
||||
14. I/O Assignment Warnings
|
||||
15. Fitter Resource Utilization by Entity
|
||||
16. Delay Chain Summary
|
||||
17. Pad To Core Delay Chain Fanout
|
||||
18. Routing Usage Summary
|
||||
19. I/O Rules Summary
|
||||
20. I/O Rules Details
|
||||
21. I/O Rules Matrix
|
||||
22. Fitter Device Options
|
||||
23. Operating Settings and Conditions
|
||||
24. Fitter Messages
|
||||
5. Ignored Assignments
|
||||
6. Incremental Compilation Preservation Summary
|
||||
7. Incremental Compilation Partition Settings
|
||||
8. Incremental Compilation Placement Preservation
|
||||
9. Pin-Out File
|
||||
10. Fitter Resource Usage Summary
|
||||
11. Fitter Partition Statistics
|
||||
12. Input Pins
|
||||
13. Output Pins
|
||||
14. I/O Bank Usage
|
||||
15. All Package Pins
|
||||
16. I/O Assignment Warnings
|
||||
17. Fitter Resource Utilization by Entity
|
||||
18. Delay Chain Summary
|
||||
19. Pad To Core Delay Chain Fanout
|
||||
20. Routing Usage Summary
|
||||
21. I/O Rules Summary
|
||||
22. I/O Rules Details
|
||||
23. I/O Rules Matrix
|
||||
24. Fitter Device Options
|
||||
25. Operating Settings and Conditions
|
||||
26. Fitter Messages
|
||||
|
||||
|
||||
|
||||
@@ -56,7 +58,7 @@ on the Quartus Prime software download page.
|
||||
+-----------------------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+---------------------------------+-------------------------------------------------+
|
||||
; Fitter Status ; Successful - Tue Oct 13 15:08:53 2026 ;
|
||||
; Fitter Status ; Successful - Tue Oct 13 16:18:53 2026 ;
|
||||
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
||||
; Revision Name ; assignment2 ;
|
||||
; Top-level Entity Name ; assignment2 ;
|
||||
@@ -65,7 +67,7 @@ on the Quartus Prime software download page.
|
||||
; Timing Models ; Final ;
|
||||
; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ;
|
||||
; Total registers ; 0 ;
|
||||
; Total pins ; 1 / 364 ( < 1 % ) ;
|
||||
; Total pins ; 40 / 364 ( 11 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
|
||||
; Total RAM Blocks ; 0 / 446 ( 0 % ) ;
|
||||
@@ -155,19 +157,28 @@ on the Quartus Prime software download page.
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------+
|
||||
; Incremental Compilation Preservation Summary ;
|
||||
+---------------------+------------------+----------------------------+--------------------------+
|
||||
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
|
||||
+---------------------+------------------+----------------------------+--------------------------+
|
||||
; Placement (by node) ; ; ; ;
|
||||
; -- Requested ; 0.00 % ( 0 / 3 ) ; 0.00 % ( 0 / 3 ) ; 0.00 % ( 0 / 3 ) ;
|
||||
; -- Achieved ; 0.00 % ( 0 / 3 ) ; 0.00 % ( 0 / 3 ) ; 0.00 % ( 0 / 3 ) ;
|
||||
; ; ; ; ;
|
||||
; Routing (by net) ; ; ; ;
|
||||
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
||||
; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
||||
+---------------------+------------------+----------------------------+--------------------------+
|
||||
+----------------------------------------------------------------------------------------------+
|
||||
; Ignored Assignments ;
|
||||
+--------------+----------------+--------------+--------------+---------------+----------------+
|
||||
; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
|
||||
+--------------+----------------+--------------+--------------+---------------+----------------+
|
||||
; I/O Standard ; assignment2 ; ; HID_Register ; 1.2 V ; QSF Assignment ;
|
||||
+--------------+----------------+--------------+--------------+---------------+----------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------+
|
||||
; Incremental Compilation Preservation Summary ;
|
||||
+---------------------+-------------------+----------------------------+--------------------------+
|
||||
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
|
||||
+---------------------+-------------------+----------------------------+--------------------------+
|
||||
; Placement (by node) ; ; ; ;
|
||||
; -- Requested ; 0.00 % ( 0 / 81 ) ; 0.00 % ( 0 / 81 ) ; 0.00 % ( 0 / 81 ) ;
|
||||
; -- Achieved ; 0.00 % ( 0 / 81 ) ; 0.00 % ( 0 / 81 ) ; 0.00 % ( 0 / 81 ) ;
|
||||
; ; ; ; ;
|
||||
; Routing (by net) ; ; ; ;
|
||||
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
||||
; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
||||
+---------------------+-------------------+----------------------------+--------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
@@ -185,7 +196,7 @@ on the Quartus Prime software download page.
|
||||
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
||||
; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
|
||||
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
||||
; Top ; 0.00 % ( 0 / 3 ) ; N/A ; Source File ; N/A ; ;
|
||||
; Top ; 0.00 % ( 0 / 81 ) ; N/A ; Source File ; N/A ; ;
|
||||
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
|
||||
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
||||
|
||||
@@ -238,7 +249,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; -- Routing optimization registers ; 0 ; ;
|
||||
; ; ; ;
|
||||
; Virtual pins ; 0 ; ;
|
||||
; I/O pins ; 1 / 364 ; < 1 % ;
|
||||
; I/O pins ; 40 / 364 ; 11 % ;
|
||||
; -- Clock pins ; 1 / 14 ; 7 % ;
|
||||
; -- Dedicated input pins ; 0 / 23 ; 0 % ;
|
||||
; ; ; ;
|
||||
@@ -273,8 +284,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; Peak interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ;
|
||||
; Maximum fan-out ; 1 ; ;
|
||||
; Highest non-global fan-out ; 1 ; ;
|
||||
; Total fan-out ; 1 ; ;
|
||||
; Average fan-out ; 0.33 ; ;
|
||||
; Total fan-out ; 40 ; ;
|
||||
; Average fan-out ; 0.49 ; ;
|
||||
+-------------------------------------------------------------+--------------------+-------+
|
||||
|
||||
|
||||
@@ -324,7 +335,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; ; ; ;
|
||||
; ; ; ;
|
||||
; Virtual pins ; 0 ; 0 ;
|
||||
; I/O pins ; 1 ; 0 ;
|
||||
; I/O pins ; 40 ; 0 ;
|
||||
; I/O registers ; 0 ; 0 ;
|
||||
; Total block memory bits ; 0 ; 0 ;
|
||||
; Total block memory implementation bits ; 0 ; 0 ;
|
||||
@@ -336,7 +347,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; -- Registered Output Connections ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Internal Connections ; ; ;
|
||||
; -- Total Connections ; 1 ; 0 ;
|
||||
; -- Total Connections ; 40 ; 0 ;
|
||||
; -- Registered Connections ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; External Connections ; ; ;
|
||||
@@ -344,8 +355,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; -- hard_block:auto_generated_inst ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Partition Interface ; ; ;
|
||||
; -- Input Ports ; 1 ; 0 ;
|
||||
; -- Output Ports ; 0 ; 0 ;
|
||||
; -- Input Ports ; 8 ; 0 ;
|
||||
; -- Output Ports ; 32 ; 0 ;
|
||||
; -- Bidir Ports ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Registered Ports ; ; ;
|
||||
@@ -364,31 +375,78 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
+-------------------------------------------------------------+---------------------+--------------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Input Pins ;
|
||||
+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
|
||||
+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
||||
; clk[0] ; M21 ; 6A ; 68 ; 32 ; 60 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Input Pins ;
|
||||
+-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
|
||||
+-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
||||
; HID_Hi_Low[0] ; AC8 ; 3B ; 14 ; 0 ; 51 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||
; HID_PC[0] ; W11 ; 3B ; 10 ; 0 ; 40 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||
; HID_Register[0] ; AB10 ; 3B ; 12 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||
; HID_Register[1] ; V10 ; 3B ; 17 ; 0 ; 74 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||
; HID_Register[2] ; AC10 ; 3B ; 12 ; 0 ; 51 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||
; HID_Register[3] ; Y11 ; 3B ; 10 ; 0 ; 57 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||
; HID_Register[4] ; AE19 ; 4A ; 50 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||
; clk[0] ; Y16 ; 4A ; 46 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||
+-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------+
|
||||
; I/O Bank Usage ;
|
||||
+----------+----------------+---------------+--------------+---------------+
|
||||
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
|
||||
+----------+----------------+---------------+--------------+---------------+
|
||||
; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
|
||||
; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
|
||||
; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 3B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 4A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 6A ; 1 / 48 ( 2 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 8A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
+----------+----------------+---------------+--------------+---------------+
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Output Pins ;
|
||||
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
|
||||
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
||||
; out_seg_0[0] ; J25 ; 6A ; 68 ; 32 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
; out_seg_0[1] ; V19 ; 4A ; 66 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_0[2] ; V18 ; 4A ; 64 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_0[3] ; V17 ; 4A ; 64 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_0[4] ; W18 ; 4A ; 66 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_0[5] ; Y20 ; 4A ; 65 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_0[6] ; Y19 ; 4A ; 65 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_0[7] ; Y18 ; 4A ; 62 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_1[0] ; D7 ; 8A ; 17 ; 61 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
; out_seg_1[1] ; AA18 ; 4A ; 62 ; 0 ; 57 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_1[2] ; AD26 ; 4A ; 64 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_1[3] ; AB19 ; 4A ; 65 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_1[4] ; AE26 ; 4A ; 64 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_1[5] ; AE25 ; 4A ; 62 ; 0 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_1[6] ; AC19 ; 4A ; 65 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_1[7] ; AF24 ; 4A ; 62 ; 0 ; 91 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_2[0] ; H18 ; 7A ; 64 ; 61 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
; out_seg_2[1] ; AD7 ; 3A ; 7 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_2[2] ; AD6 ; 3A ; 7 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_2[3] ; U20 ; 5A ; 68 ; 13 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_2[4] ; V22 ; 5A ; 68 ; 12 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_2[5] ; V20 ; 5A ; 68 ; 10 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_2[6] ; W21 ; 5A ; 68 ; 11 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_2[7] ; W20 ; 5A ; 68 ; 11 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_3[0] ; H14 ; 7A ; 53 ; 61 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
; out_seg_3[1] ; Y24 ; 5A ; 68 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_3[2] ; Y23 ; 5A ; 68 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_3[3] ; AA23 ; 5A ; 68 ; 11 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_3[4] ; AA22 ; 5A ; 68 ; 11 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_3[5] ; AC24 ; 5A ; 68 ; 12 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_3[6] ; AC23 ; 5A ; 68 ; 10 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
; out_seg_3[7] ; AC22 ; 5A ; 68 ; 10 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; I/O Bank Usage ;
|
||||
+----------+------------------+---------------+--------------+---------------+
|
||||
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
|
||||
+----------+------------------+---------------+--------------+---------------+
|
||||
; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
|
||||
; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
|
||||
; 3A ; 2 / 16 ( 13 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 3B ; 6 / 32 ( 19 % ) ; 1.2V ; -- ; 2.5V ;
|
||||
; 4A ; 16 / 80 ( 20 % ) ; 1.2V ; -- ; 2.5V ;
|
||||
; 5A ; 12 / 16 ( 75 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 6A ; 1 / 48 ( 2 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 7A ; 2 / 80 ( 3 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 8A ; 1 / 32 ( 3 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
+----------+------------------+---------------+--------------+---------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
@@ -429,7 +487,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; AA7 ; 47 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AA8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AA9 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
|
||||
; AA10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AA10 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; AA11 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AA12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
; AA13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
@@ -437,12 +495,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; AA15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AA16 ; 113 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AA17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AA18 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AA18 ; 151 ; 4A ; out_seg_1[1] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; AA19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AA20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AA20 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; AA21 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AA22 ; 170 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; AA23 ; 172 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; AA22 ; 170 ; 5A ; out_seg_3[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
|
||||
; AA23 ; 172 ; 5A ; out_seg_3[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
|
||||
; AA24 ; 187 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; AA25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AA26 ; 201 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
@@ -455,16 +513,16 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; AB7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
; AB8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AB9 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AB10 ; 61 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AB10 ; 61 ; 3B ; HID_Register[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; AB11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AB12 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AB13 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AB13 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; AB14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AB15 ; 105 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AB16 ; 111 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AB17 ; 129 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AB18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AB19 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AB19 ; 160 ; 4A ; out_seg_1[3] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; AB20 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AB21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AB22 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
@@ -479,23 +537,23 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; AC5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AC6 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AC7 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
|
||||
; AC8 ; 62 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AC8 ; 62 ; 3B ; HID_Hi_Low[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; AC9 ; 64 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AC10 ; 59 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AC10 ; 59 ; 3B ; HID_Register[2] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; AC11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AC12 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
|
||||
; AC13 ; 102 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AC14 ; 104 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AC15 ; 103 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AC16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AC16 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; AC17 ; 127 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AC18 ; 120 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AC19 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AC19 ; 158 ; 4A ; out_seg_1[6] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; AC20 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AC21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AC22 ; 166 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; AC23 ; 168 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; AC24 ; 174 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; AC22 ; 166 ; 5A ; out_seg_3[7] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
|
||||
; AC23 ; 168 ; 5A ; out_seg_3[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
|
||||
; AC24 ; 174 ; 5A ; out_seg_3[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
|
||||
; AC25 ; 193 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AD1 ; 25 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ;
|
||||
@@ -503,10 +561,10 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; AD3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AD4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AD5 ; 35 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
|
||||
; AD6 ; 51 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD7 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD6 ; 51 ; 3A ; out_seg_2[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; AD7 ; 53 ; 3A ; out_seg_2[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; AD8 ; 73 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD9 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AD9 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; AD10 ; 96 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD11 ; 88 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD12 ; 91 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
@@ -516,14 +574,14 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; AD16 ; 119 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD17 ; 121 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD18 ; 118 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AD19 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; AD20 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD21 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD22 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD23 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AD25 ; 191 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; AD26 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD26 ; 157 ; 4A ; out_seg_1[2] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AE3 ; 22 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
@@ -535,21 +593,21 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; AE9 ; 77 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AE10 ; 94 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AE11 ; 86 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AE12 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AE12 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; AE13 ; 109 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AE14 ; 112 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AE15 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AE16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AE17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AE18 ; 117 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AE19 ; 125 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AE19 ; 125 ; 4A ; HID_Register[4] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; AE20 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AE21 ; 131 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AE22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AE22 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; AE23 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AE24 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AE25 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AE26 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AE25 ; 152 ; 4A ; out_seg_1[5] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; AE26 ; 155 ; 4A ; out_seg_1[4] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AF4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
@@ -563,7 +621,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; AF12 ; 99 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF13 ; 107 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF14 ; 110 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF15 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AF15 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; AF16 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF17 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF18 ; 115 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
@@ -572,7 +630,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; AF21 ; 128 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF22 ; 126 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF23 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF24 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF24 ; 150 ; 4A ; out_seg_1[7] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; AF25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; B1 ; ; ; RREF ; ; ; ; -- ; ; -- ; -- ;
|
||||
; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
@@ -632,7 +690,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; D5 ; 395 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
|
||||
; D6 ; 352 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; D7 ; 356 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; D7 ; 356 ; 8A ; out_seg_1[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; D8 ; 372 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; D9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; D10 ; 316 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
@@ -743,11 +801,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; H11 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; H12 ; 327 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; H13 ; 297 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; H14 ; 295 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; H14 ; 295 ; 7A ; out_seg_3[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; H15 ; 263 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; H16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; H17 ; 273 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; H18 ; 271 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; H18 ; 271 ; 7A ; out_seg_2[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; H19 ; 250 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; H20 ; 252 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; H21 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
@@ -780,7 +838,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; J22 ; ; 6A ; VCCPD6A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; J23 ; 244 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; J24 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; J25 ; 215 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; J25 ; 215 ; 6A ; out_seg_0[0] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
|
||||
; J26 ; 217 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; K1 ; 2 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
; K2 ; 3 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
@@ -854,7 +912,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; M18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
||||
; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; M20 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
||||
; M21 ; 216 ; 6A ; clk[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
|
||||
; M21 ; 216 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; M22 ; 224 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; M23 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; M24 ; 220 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
@@ -971,7 +1029,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; U5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
||||
; U6 ; 31 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
|
||||
; U7 ; 39 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; U8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; U8 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; U9 ; 54 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; U10 ; 81 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; U11 ; 79 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
@@ -981,9 +1039,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; U15 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; U16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; U17 ; 130 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; U18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; U18 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; U19 ; 167 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; U20 ; 181 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; U20 ; 181 ; 5A ; out_seg_2[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
|
||||
; U21 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; U22 ; 177 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; U23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
@@ -999,19 +1057,19 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; V7 ; 28 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
|
||||
; V8 ; 41 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; V9 ; 70 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; V10 ; 72 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; V11 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; V10 ; 72 ; 3B ; HID_Register[1] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; V11 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; V12 ; 98 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; V13 ; 92 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; V14 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; V15 ; 124 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; V18 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; V19 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; V20 ; 169 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; V17 ; 154 ; 4A ; out_seg_0[3] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; V18 ; 156 ; 4A ; out_seg_0[2] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; V19 ; 164 ; 4A ; out_seg_0[1] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; V20 ; 169 ; 5A ; out_seg_2[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
|
||||
; V21 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; V22 ; 175 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; V22 ; 175 ; 5A ; out_seg_2[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
|
||||
; V23 ; 183 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; V24 ; 185 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; V25 ; 197 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
@@ -1026,17 +1084,17 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; W8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; W10 ; 69 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W11 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W11 ; 57 ; 3B ; HID_PC[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; W12 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W14 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; W14 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; W15 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W17 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W18 ; 162 ; 4A ; out_seg_0[4] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; W20 ; 171 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; W21 ; 173 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; W20 ; 171 ; 5A ; out_seg_2[7] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
|
||||
; W21 ; 173 ; 5A ; out_seg_2[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
|
||||
; W22 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
|
||||
; W23 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;
|
||||
; W24 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
@@ -1052,34 +1110,68 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; Y8 ; 49 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y9 ; 44 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y10 ; 67 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y11 ; 55 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y11 ; 55 ; 3B ; HID_Register[3] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; Y13 ; 95 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y14 ; 89 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y15 ; 116 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y16 ; 114 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; Y18 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y20 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y16 ; 114 ; 4A ; clk[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; Y17 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; Y18 ; 153 ; 4A ; out_seg_0[7] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; Y19 ; 159 ; 4A ; out_seg_0[6] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; Y20 ; 161 ; 4A ; out_seg_0[5] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; Y21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; Y22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; Y23 ; 178 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; Y24 ; 180 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; Y23 ; 178 ; 5A ; out_seg_3[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
|
||||
; Y24 ; 180 ; 5A ; out_seg_3[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
|
||||
; Y25 ; 203 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; Y26 ; 205 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
+----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
|
||||
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; I/O Assignment Warnings ;
|
||||
+----------+-------------------------------+
|
||||
; Pin Name ; Reason ;
|
||||
+----------+-------------------------------+
|
||||
; clk[0] ; Incomplete set of assignments ;
|
||||
; clk[0] ; Missing location assignment ;
|
||||
+----------+-------------------------------+
|
||||
+-----------------------------------------------------+
|
||||
; I/O Assignment Warnings ;
|
||||
+--------------+--------------------------------------+
|
||||
; Pin Name ; Reason ;
|
||||
+--------------+--------------------------------------+
|
||||
; out_seg_0[0] ; Incomplete set of assignments ;
|
||||
; out_seg_0[1] ; Missing drive strength and slew rate ;
|
||||
; out_seg_0[2] ; Missing drive strength and slew rate ;
|
||||
; out_seg_0[3] ; Missing drive strength and slew rate ;
|
||||
; out_seg_0[4] ; Missing drive strength and slew rate ;
|
||||
; out_seg_0[5] ; Missing drive strength and slew rate ;
|
||||
; out_seg_0[6] ; Missing drive strength and slew rate ;
|
||||
; out_seg_0[7] ; Missing drive strength and slew rate ;
|
||||
; out_seg_1[0] ; Incomplete set of assignments ;
|
||||
; out_seg_1[1] ; Missing drive strength and slew rate ;
|
||||
; out_seg_1[2] ; Missing drive strength and slew rate ;
|
||||
; out_seg_1[3] ; Missing drive strength and slew rate ;
|
||||
; out_seg_1[4] ; Missing drive strength and slew rate ;
|
||||
; out_seg_1[5] ; Missing drive strength and slew rate ;
|
||||
; out_seg_1[6] ; Missing drive strength and slew rate ;
|
||||
; out_seg_1[7] ; Missing drive strength and slew rate ;
|
||||
; out_seg_2[0] ; Incomplete set of assignments ;
|
||||
; out_seg_2[1] ; Incomplete set of assignments ;
|
||||
; out_seg_2[2] ; Incomplete set of assignments ;
|
||||
; out_seg_2[3] ; Incomplete set of assignments ;
|
||||
; out_seg_2[4] ; Incomplete set of assignments ;
|
||||
; out_seg_2[5] ; Incomplete set of assignments ;
|
||||
; out_seg_2[6] ; Incomplete set of assignments ;
|
||||
; out_seg_2[7] ; Incomplete set of assignments ;
|
||||
; out_seg_3[0] ; Incomplete set of assignments ;
|
||||
; out_seg_3[1] ; Incomplete set of assignments ;
|
||||
; out_seg_3[2] ; Incomplete set of assignments ;
|
||||
; out_seg_3[3] ; Incomplete set of assignments ;
|
||||
; out_seg_3[4] ; Incomplete set of assignments ;
|
||||
; out_seg_3[5] ; Incomplete set of assignments ;
|
||||
; out_seg_3[6] ; Incomplete set of assignments ;
|
||||
; out_seg_3[7] ; Incomplete set of assignments ;
|
||||
; out_seg_0[0] ; Missing location assignment ;
|
||||
; out_seg_1[0] ; Missing location assignment ;
|
||||
; out_seg_2[0] ; Missing location assignment ;
|
||||
; out_seg_3[0] ; Missing location assignment ;
|
||||
+--------------+--------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
@@ -1087,18 +1179,57 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
|
||||
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
|
||||
; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
|
||||
; |assignment2 ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 1 ; 0 ; |assignment2 ; assignment2 ; work ;
|
||||
; |assignment2 ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 40 ; 0 ; |assignment2 ; assignment2 ; work ;
|
||||
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------+
|
||||
; Delay Chain Summary ;
|
||||
+--------+----------+----+------+------+----+----+-------+--------+------------------------+--------------------------+
|
||||
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
|
||||
+--------+----------+----+------+------+----+----+-------+--------+------------------------+--------------------------+
|
||||
; clk[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
+--------+----------+----+------+------+----+----+-------+--------+------------------------+--------------------------+
|
||||
+--------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Delay Chain Summary ;
|
||||
+-----------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
||||
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
|
||||
+-----------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
||||
; clk[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; HID_Register[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; HID_Register[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; HID_Register[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; HID_Register[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; HID_Register[4] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; HID_PC[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; HID_Hi_Low[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; out_seg_0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_0[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_2[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_2[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_2[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_2[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_2[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_2[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_2[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_3[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_3[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_3[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_3[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_3[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_3[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_3[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_3[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
+-----------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------+
|
||||
@@ -1107,6 +1238,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
|
||||
+---------------------+-------------------+---------+
|
||||
; clk[0] ; ; ;
|
||||
; HID_Register[0] ; ; ;
|
||||
; HID_Register[1] ; ; ;
|
||||
; HID_Register[2] ; ; ;
|
||||
; HID_Register[3] ; ; ;
|
||||
; HID_Register[4] ; ; ;
|
||||
; HID_PC[0] ; ; ;
|
||||
; HID_Hi_Low[0] ; ; ;
|
||||
+---------------------+-------------------+---------+
|
||||
|
||||
|
||||
@@ -1142,47 +1280,48 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; I/O Rules Statistic ; Total ;
|
||||
+----------------------------------+-------+
|
||||
; Total I/O Rules ; 28 ;
|
||||
; Number of I/O Rules Passed ; 3 ;
|
||||
; Number of I/O Rules Passed ; 9 ;
|
||||
; Number of I/O Rules Failed ; 0 ;
|
||||
; Number of I/O Rules Unchecked ; 0 ;
|
||||
; Number of I/O Rules Inapplicable ; 25 ;
|
||||
; Number of I/O Rules Inapplicable ; 19 ;
|
||||
+----------------------------------+-------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; I/O Rules Details ;
|
||||
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+-------------------------------------------------------------------------------------------+------+-------------------+
|
||||
; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
|
||||
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+-------------------------------------------------------------------------------------------+------+-------------------+
|
||||
; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
|
||||
; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
|
||||
; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Outputs with single-ended I/O Standard or Differential I/O Standard assignments found. ; I/O ; ;
|
||||
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+-------------------------------------------------------------------------------------------+------+-------------------+
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; I/O Rules Details ;
|
||||
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
|
||||
; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
|
||||
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
|
||||
; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
|
||||
; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
|
||||
; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
|
||||
; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
|
||||
; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
|
||||
; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
|
||||
; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
|
||||
; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
|
||||
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
@@ -1190,11 +1329,50 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
|
||||
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; 0 ;
|
||||
; Total Pass ; 0 ; 36 ; 36 ; 0 ; 0 ; 40 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 32 ; 0 ; 40 ; 40 ; 0 ;
|
||||
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; Total Inapplicable ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 1 ;
|
||||
; Total Inapplicable ; 40 ; 4 ; 4 ; 40 ; 40 ; 0 ; 4 ; 40 ; 40 ; 40 ; 40 ; 40 ; 40 ; 8 ; 40 ; 40 ; 40 ; 40 ; 8 ; 40 ; 40 ; 40 ; 40 ; 8 ; 40 ; 0 ; 0 ; 40 ;
|
||||
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; clk[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; clk[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; HID_Register[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; HID_Register[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; HID_Register[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; HID_Register[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; HID_Register[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; HID_PC[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; HID_Hi_Low[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_0[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_0[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_0[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_0[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_0[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_0[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_0[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_0[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_2[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_2[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_2[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_2[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_2[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_2[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_2[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_2[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_3[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_3[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_3[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_3[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_3[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_3[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_3[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_3[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
|
||||
|
||||
@@ -1252,7 +1430,7 @@ Info (21077): High junction temperature is 85 degrees C
|
||||
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
|
||||
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
|
||||
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
|
||||
Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 1 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
|
||||
Critical Warning (169085): No exact pin location assignment(s) for 4 pins of 40 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
|
||||
Info (184020): Starting Fitter periphery placement operations
|
||||
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
|
||||
Info (176233): Starting register packing
|
||||
@@ -1268,7 +1446,7 @@ Info (332154): The derive_clock_uncertainty command did not apply clock uncertai
|
||||
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
|
||||
Info (170189): Fitter placement preparation operations beginning
|
||||
Info (14951): The Fitter is using Advanced Physical Optimization.
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
|
||||
Info (170191): Fitter placement operations beginning
|
||||
Info (170137): Fitter placement was successful
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
|
||||
@@ -1284,11 +1462,12 @@ Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:02
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
|
||||
Info: Peak virtual memory: 1336 megabytes
|
||||
Info: Processing ended: Tue Oct 13 15:08:54 2026
|
||||
Info: Elapsed time: 00:00:25
|
||||
Info: Total CPU time (on all processors): 00:00:36
|
||||
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:05
|
||||
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 7 warnings
|
||||
Info: Peak virtual memory: 1337 megabytes
|
||||
Info: Processing ended: Tue Oct 13 16:18:53 2026
|
||||
Info: Elapsed time: 00:00:30
|
||||
Info: Total CPU time (on all processors): 00:00:42
|
||||
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
Fitter Status : Successful - Tue Oct 13 15:08:53 2026
|
||||
Fitter Status : Successful - Tue Oct 13 16:18:53 2026
|
||||
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Revision Name : assignment2
|
||||
Top-level Entity Name : assignment2
|
||||
@@ -7,7 +7,7 @@ Device : 5CGXFC5C6F27C7
|
||||
Timing Models : Final
|
||||
Logic utilization (in ALMs) : 1 / 29,080 ( < 1 % )
|
||||
Total registers : 0
|
||||
Total pins : 1 / 364 ( < 1 % )
|
||||
Total pins : 40 / 364 ( 11 % )
|
||||
Total virtual pins : 0
|
||||
Total block memory bits : 0 / 4,567,040 ( 0 % )
|
||||
Total RAM Blocks : 0 / 446 ( 0 % )
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
Flow report for assignment2
|
||||
Tue Oct 13 15:09:08 2026
|
||||
Tue Oct 13 16:19:10 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
@@ -41,7 +41,7 @@ on the Quartus Prime software download page.
|
||||
+-----------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+---------------------------------+-------------------------------------------------+
|
||||
; Flow Status ; Successful - Tue Oct 13 15:09:08 2026 ;
|
||||
; Flow Status ; Successful - Tue Oct 13 16:19:10 2026 ;
|
||||
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
||||
; Revision Name ; assignment2 ;
|
||||
; Top-level Entity Name ; assignment2 ;
|
||||
@@ -50,7 +50,7 @@ on the Quartus Prime software download page.
|
||||
; Timing Models ; Final ;
|
||||
; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ;
|
||||
; Total registers ; 0 ;
|
||||
; Total pins ; 1 / 364 ( < 1 % ) ;
|
||||
; Total pins ; 40 / 364 ( 11 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
|
||||
; Total DSP Blocks ; 0 / 150 ( 0 % ) ;
|
||||
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 10/13/2026 15:08:18 ;
|
||||
; Start date & time ; 10/13/2026 16:18:11 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; assignment2 ;
|
||||
+-------------------+---------------------+
|
||||
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
|
||||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||
; COMPILER_SIGNATURE_ID ; 117114050183607.179186449807774 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 117114050183607.179186869111054 ; -- ; -- ; -- ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
|
||||
@@ -102,12 +102,12 @@ on the Quartus Prime software download page.
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 412 MB ; 00:00:24 ;
|
||||
; Fitter ; 00:00:24 ; 1.0 ; 1336 MB ; 00:00:36 ;
|
||||
; Assembler ; 00:00:06 ; 1.0 ; 521 MB ; 00:00:05 ;
|
||||
; Timing Analyzer ; 00:00:04 ; 1.0 ; 718 MB ; 00:00:04 ;
|
||||
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 659 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:46 ; -- ; -- ; 00:01:10 ;
|
||||
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 410 MB ; 00:00:25 ;
|
||||
; Fitter ; 00:00:30 ; 1.0 ; 1337 MB ; 00:00:42 ;
|
||||
; Assembler ; 00:00:06 ; 1.0 ; 508 MB ; 00:00:06 ;
|
||||
; Timing Analyzer ; 00:00:05 ; 1.0 ; 757 MB ; 00:00:05 ;
|
||||
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 670 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:53 ; -- ; -- ; 00:01:19 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
Analysis & Synthesis report for assignment2
|
||||
Tue Oct 13 15:08:28 2026
|
||||
Tue Oct 13 16:18:22 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
@@ -23,15 +23,20 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
15. Parameter Settings for User Entity Instance: alu:ALU|asu:adder_unit
|
||||
16. Parameter Settings for User Entity Instance: alu:ALU|lu:logic_unit
|
||||
17. Parameter Settings for User Entity Instance: shifter:SHIFTER
|
||||
18. Port Connectivity Checks: "shifter:SHIFTER"
|
||||
19. Port Connectivity Checks: "alu:ALU"
|
||||
20. Port Connectivity Checks: "register_file:REGS"
|
||||
21. Port Connectivity Checks: "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER"
|
||||
22. Port Connectivity Checks: "instruction_classifier:INSTRUCTION_CLASSIFIER"
|
||||
23. Port Connectivity Checks: "instruction_counter:PC"
|
||||
24. Post-Synthesis Netlist Statistics for Top Partition
|
||||
25. Elapsed Time Per Partition
|
||||
26. Analysis & Synthesis Messages
|
||||
18. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit3"
|
||||
19. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit2"
|
||||
20. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit1"
|
||||
21. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit0"
|
||||
22. Port Connectivity Checks: "seven_seg_4digit:display"
|
||||
23. Port Connectivity Checks: "shifter:SHIFTER"
|
||||
24. Port Connectivity Checks: "alu:ALU"
|
||||
25. Port Connectivity Checks: "register_file:REGS"
|
||||
26. Port Connectivity Checks: "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER"
|
||||
27. Port Connectivity Checks: "instruction_classifier:INSTRUCTION_CLASSIFIER"
|
||||
28. Port Connectivity Checks: "instruction_counter:PC"
|
||||
29. Post-Synthesis Netlist Statistics for Top Partition
|
||||
30. Elapsed Time Per Partition
|
||||
31. Analysis & Synthesis Messages
|
||||
|
||||
|
||||
|
||||
@@ -58,14 +63,14 @@ on the Quartus Prime software download page.
|
||||
+-----------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+---------------------------------+-------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Tue Oct 13 15:08:28 2026 ;
|
||||
; Analysis & Synthesis Status ; Successful - Tue Oct 13 16:18:22 2026 ;
|
||||
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
||||
; Revision Name ; assignment2 ;
|
||||
; Top-level Entity Name ; assignment2 ;
|
||||
; Family ; Cyclone V ;
|
||||
; Logic utilization (in ALMs) ; N/A ;
|
||||
; Total registers ; 0 ;
|
||||
; Total pins ; 1 ;
|
||||
; Total pins ; 40 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total block memory bits ; 0 ;
|
||||
; Total DSP Blocks ; 0 ;
|
||||
@@ -197,6 +202,8 @@ on the Quartus Prime software download page.
|
||||
; ../../modules/lu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv ; ;
|
||||
; ../../modules/alu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv ; ;
|
||||
; ../../modules/shifter.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv ; ;
|
||||
; ../../modules/seven_seg.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv ; ;
|
||||
; ../../modules/seven_seg_4digit.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv ; ;
|
||||
; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt ; yes ; Auto-Found File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt ; ;
|
||||
+----------------------------------------------------------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+
|
||||
|
||||
@@ -217,13 +224,13 @@ on the Quartus Prime software download page.
|
||||
; ; ;
|
||||
; Dedicated logic registers ; 0 ;
|
||||
; ; ;
|
||||
; I/O pins ; 1 ;
|
||||
; I/O pins ; 40 ;
|
||||
; ; ;
|
||||
; Total DSP Blocks ; 0 ;
|
||||
; ; ;
|
||||
; Maximum fan-out node ; clk[0] ;
|
||||
; Maximum fan-out ; 1 ;
|
||||
; Total fan-out ; 1 ;
|
||||
; Total fan-out ; 40 ;
|
||||
; Average fan-out ; 0.50 ;
|
||||
+---------------------------------------------+--------+
|
||||
|
||||
@@ -233,7 +240,7 @@ on the Quartus Prime software download page.
|
||||
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
|
||||
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
|
||||
; |assignment2 ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; |assignment2 ; assignment2 ; work ;
|
||||
; |assignment2 ; 0 (0) ; 0 (0) ; 0 ; 0 ; 40 ; 0 ; |assignment2 ; assignment2 ; work ;
|
||||
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
@@ -347,6 +354,58 @@ Note: In order to hide this table in the UI and the text report file, please set
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit3" ;
|
||||
+---------+-------+----------+------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+---------+-------+----------+------------------------------------------+
|
||||
; rbi_inv ; Input ; Info ; Stuck at GND ;
|
||||
+---------+-------+----------+------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit2" ;
|
||||
+---------+-------+----------+------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+---------+-------+----------+------------------------------------------+
|
||||
; rbi_inv ; Input ; Info ; Stuck at GND ;
|
||||
+---------+-------+----------+------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit1" ;
|
||||
+---------+-------+----------+------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+---------+-------+----------+------------------------------------------+
|
||||
; rbi_inv ; Input ; Info ; Stuck at GND ;
|
||||
+---------+-------+----------+------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit0" ;
|
||||
+---------+-------+----------+------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+---------+-------+----------+------------------------------------------+
|
||||
; rbi_inv ; Input ; Info ; Stuck at GND ;
|
||||
+---------+-------+----------+------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------+
|
||||
; Port Connectivity Checks: "seven_seg_4digit:display" ;
|
||||
+-------------+-------+----------+---------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+-------------+-------+----------+---------------------+
|
||||
; num[15..14] ; Input ; Info ; Stuck at VCC ;
|
||||
; num[9..8] ; Input ; Info ; Stuck at VCC ;
|
||||
; num[13..10] ; Input ; Info ; Stuck at GND ;
|
||||
; num[5..2] ; Input ; Info ; Stuck at GND ;
|
||||
; num[7] ; Input ; Info ; Stuck at GND ;
|
||||
; num[6] ; Input ; Info ; Stuck at VCC ;
|
||||
; num[1] ; Input ; Info ; Stuck at VCC ;
|
||||
; num[0] ; Input ; Info ; Stuck at GND ;
|
||||
+-------------+-------+----------+---------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "shifter:SHIFTER" ;
|
||||
+-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
@@ -415,14 +474,17 @@ Note: In order to hide this table in the UI and the text report file, please set
|
||||
|
||||
+-----------------------------------------------------+
|
||||
; Post-Synthesis Netlist Statistics for Top Partition ;
|
||||
+-------------------+---------------------------------+
|
||||
; Type ; Count ;
|
||||
+-------------------+---------------------------------+
|
||||
; boundary_port ; 1 ;
|
||||
; ; ;
|
||||
; Max LUT depth ; 0.00 ;
|
||||
; Average LUT depth ; 0.00 ;
|
||||
+-------------------+---------------------------------+
|
||||
+-----------------------+-----------------------------+
|
||||
; Type ; Count ;
|
||||
+-----------------------+-----------------------------+
|
||||
; arriav_lcell_comb ; 2 ;
|
||||
; normal ; 2 ;
|
||||
; 0 data inputs ; 2 ;
|
||||
; boundary_port ; 40 ;
|
||||
; ; ;
|
||||
; Max LUT depth ; 0.00 ;
|
||||
; Average LUT depth ; 0.00 ;
|
||||
+-----------------------+-----------------------------+
|
||||
|
||||
|
||||
+-------------------------------+
|
||||
@@ -440,11 +502,11 @@ Note: In order to hide this table in the UI and the text report file, please set
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Info: Processing started: Tue Oct 13 15:08:17 2026
|
||||
Info: Processing started: Tue Oct 13 16:18:11 2026
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
||||
Info (12021): Found 11 design units, including 11 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv
|
||||
Info (12021): Found 13 design units, including 13 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv
|
||||
Info (12023): Found entity 1: rom File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 4
|
||||
Info (12023): Found entity 2: ram File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 4
|
||||
Info (12023): Found entity 3: register_file File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv Line: 4
|
||||
@@ -455,200 +517,244 @@ Info (12021): Found 11 design units, including 11 entities, in source file /home
|
||||
Info (12023): Found entity 8: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 3
|
||||
Info (12023): Found entity 9: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 9
|
||||
Info (12023): Found entity 10: shifter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv Line: 3
|
||||
Info (12023): Found entity 11: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 15
|
||||
Info (12023): Found entity 11: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv Line: 3
|
||||
Info (12023): Found entity 12: seven_seg_4digit File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv Line: 5
|
||||
Info (12023): Found entity 13: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 15
|
||||
Info (12127): Elaborating entity "assignment2" for the top level hierarchy
|
||||
Warning (10036): Verilog HDL or VHDL warning at assignment2.sv(37): object "rd" assigned a value but never read File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 37
|
||||
Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 40
|
||||
Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 41
|
||||
Warning (10036): Verilog HDL or VHDL warning at assignment2.sv(54): object "rd" assigned a value but never read File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 54
|
||||
Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 57
|
||||
Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 59
|
||||
Warning (10850): Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range [0:1023] File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 16
|
||||
Warning (10030): Net "mem.data_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
|
||||
Warning (10030): Net "mem.waddr_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
|
||||
Warning (10030): Net "mem.we_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
|
||||
Info (12128): Elaborating entity "instruction_classifier" for hierarchy "instruction_classifier:INSTRUCTION_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 42
|
||||
Info (12128): Elaborating entity "instruction_module_classifier" for hierarchy "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 43
|
||||
Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 49
|
||||
Info (12128): Elaborating entity "alu" for hierarchy "alu:ALU" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Info (12128): Elaborating entity "instruction_classifier" for hierarchy "instruction_classifier:INSTRUCTION_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 61
|
||||
Info (12128): Elaborating entity "instruction_module_classifier" for hierarchy "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 68
|
||||
Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 74
|
||||
Info (12128): Elaborating entity "alu" for hierarchy "alu:ALU" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 77
|
||||
Info (12128): Elaborating entity "asu" for hierarchy "alu:ALU|asu:adder_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 18
|
||||
Info (12128): Elaborating entity "lu" for hierarchy "alu:ALU|lu:logic_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 21
|
||||
Info (12128): Elaborating entity "shifter" for hierarchy "shifter:SHIFTER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 55
|
||||
Info (12128): Elaborating entity "shifter" for hierarchy "shifter:SHIFTER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 80
|
||||
Info (12128): Elaborating entity "seven_seg_4digit" for hierarchy "seven_seg_4digit:display" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 93
|
||||
Info (12128): Elaborating entity "seven_seg" for hierarchy "seven_seg_4digit:display|seven_seg:digit0" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv Line: 18
|
||||
Warning (12011): Net is missing source, defaulting to GND
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12011): Net is missing source, defaulting to GND
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12011): Net is missing source, defaulting to GND
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12011): Net is missing source, defaulting to GND
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12011): Net is missing source, defaulting to GND
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
|
||||
Warning (13024): Output pins are stuck at VCC or GND
|
||||
Warning (13410): Pin "out_seg_0[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_0[1]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_0[2]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_0[3]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_0[4]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_0[5]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_0[6]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_0[7]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_1[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_1[1]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_1[2]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_1[3]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_1[4]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_1[5]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_1[6]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_1[7]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_2[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_2[1]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_2[2]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_2[3]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_2[4]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_2[5]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_2[6]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_2[7]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_3[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Warning (13410): Pin "out_seg_3[1]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Warning (13410): Pin "out_seg_3[2]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Warning (13410): Pin "out_seg_3[3]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Warning (13410): Pin "out_seg_3[4]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Warning (13410): Pin "out_seg_3[5]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Warning (13410): Pin "out_seg_3[6]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Warning (13410): Pin "out_seg_3[7]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Info (17049): 32 registers lost all their fanouts during netlist optimizations.
|
||||
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
||||
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
|
||||
Warning (21074): Design contains 1 input pin(s) that do not drive logic
|
||||
Warning (15610): No output dependent on input pin "clk[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 15
|
||||
Info (21057): Implemented 1 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 1 input pins
|
||||
Info (21059): Implemented 0 output pins
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 174 warnings
|
||||
Info: Peak virtual memory: 425 megabytes
|
||||
Info: Processing ended: Tue Oct 13 15:08:28 2026
|
||||
Warning (21074): Design contains 8 input pin(s) that do not drive logic
|
||||
Warning (15610): No output dependent on input pin "clk[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 16
|
||||
Warning (15610): No output dependent on input pin "HID_Register[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 17
|
||||
Warning (15610): No output dependent on input pin "HID_Register[1]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 17
|
||||
Warning (15610): No output dependent on input pin "HID_Register[2]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 17
|
||||
Warning (15610): No output dependent on input pin "HID_Register[3]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 17
|
||||
Warning (15610): No output dependent on input pin "HID_Register[4]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 17
|
||||
Warning (15610): No output dependent on input pin "HID_PC[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 18
|
||||
Warning (15610): No output dependent on input pin "HID_Hi_Low[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 19
|
||||
Info (21057): Implemented 40 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 8 input pins
|
||||
Info (21059): Implemented 32 output pins
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 214 warnings
|
||||
Info: Peak virtual memory: 423 megabytes
|
||||
Info: Processing ended: Tue Oct 13 16:18:22 2026
|
||||
Info: Elapsed time: 00:00:11
|
||||
Info: Total CPU time (on all processors): 00:00:24
|
||||
Info: Total CPU time (on all processors): 00:00:25
|
||||
|
||||
|
||||
@@ -1,11 +1,11 @@
|
||||
Analysis & Synthesis Status : Successful - Tue Oct 13 15:08:28 2026
|
||||
Analysis & Synthesis Status : Successful - Tue Oct 13 16:18:22 2026
|
||||
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Revision Name : assignment2
|
||||
Top-level Entity Name : assignment2
|
||||
Family : Cyclone V
|
||||
Logic utilization (in ALMs) : N/A
|
||||
Total registers : 0
|
||||
Total pins : 1
|
||||
Total pins : 40
|
||||
Total virtual pins : 0
|
||||
Total block memory bits : 0
|
||||
Total DSP Blocks : 0
|
||||
|
||||
@@ -29,8 +29,8 @@
|
||||
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
|
||||
-- of its bank.
|
||||
-- Bank 3A: 2.5V
|
||||
-- Bank 3B: 2.5V
|
||||
-- Bank 4A: 2.5V
|
||||
-- Bank 3B: 1.2V
|
||||
-- Bank 4A: 1.2V
|
||||
-- Bank 5A: 2.5V
|
||||
-- Bank 5B: 2.5V
|
||||
-- Bank 6A: 2.5V
|
||||
@@ -109,7 +109,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3A :
|
||||
VCC_AUX : AA8 : power : : 2.5V : :
|
||||
VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : :
|
||||
VCCIO3B : AA10 : power : : 2.5V : 3B :
|
||||
VCCIO3B : AA10 : power : : 1.2V : 3B :
|
||||
VCCPD3B4A : AA11 : power : : 2.5V : 3B, 4A :
|
||||
NC : AA12 : : : : :
|
||||
VCCPD3B4A : AA13 : power : : 2.5V : 3B, 4A :
|
||||
@@ -117,12 +117,12 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : :
|
||||
GND : AA15 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
|
||||
VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
|
||||
out_seg_1[1] : AA18 : output : 1.2 V : : 4A : Y
|
||||
VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A :
|
||||
VCCIO4A : AA20 : power : : 2.5V : 4A :
|
||||
VCCIO4A : AA20 : power : : 1.2V : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A :
|
||||
out_seg_3[4] : AA22 : output : 2.5 V : : 5A : Y
|
||||
out_seg_3[3] : AA23 : output : 2.5 V : : 5A : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5B :
|
||||
GND : AA25 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B :
|
||||
@@ -135,16 +135,16 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : :
|
||||
NC : AB7 : : : : :
|
||||
GND : AB8 : gnd : : : :
|
||||
VCCPD3A : AB9 : power : : 2.5V : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3B :
|
||||
HID_Register[0] : AB10 : input : 1.2 V : : 3B : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B :
|
||||
VCCIO4A : AB13 : power : : 2.5V : 4A :
|
||||
VCCIO4A : AB13 : power : : 1.2V : 4A :
|
||||
VCC_AUX : AB14 : power : : 2.5V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
|
||||
GND : AB18 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4A :
|
||||
out_seg_1[3] : AB19 : output : 1.2 V : : 4A : Y
|
||||
VCC_AUX : AB20 : power : : 2.5V : :
|
||||
VCCPD3B4A : AB21 : power : : 2.5V : 3B, 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4A :
|
||||
@@ -159,23 +159,23 @@ GXB_NC : AC4 : : :
|
||||
GND : AC5 : gnd : : : :
|
||||
VCCIO3A : AC6 : power : : 2.5V : 3A :
|
||||
VREFB3AN0 : AC7 : power : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3B :
|
||||
HID_Hi_Low[0] : AC8 : input : 1.2 V : : 3B : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3B :
|
||||
HID_Register[2] : AC10 : input : 1.2 V : : 3B : Y
|
||||
GND : AC11 : gnd : : : :
|
||||
VREFB3BN0 : AC12 : power : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC13 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4A :
|
||||
VCCIO4A : AC16 : power : : 2.5V : 4A :
|
||||
VCCIO4A : AC16 : power : : 1.2V : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4A :
|
||||
out_seg_1[6] : AC19 : output : 1.2 V : : 4A : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A :
|
||||
GND : AC21 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 5A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 5A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5A :
|
||||
out_seg_3[7] : AC22 : output : 2.5 V : : 5A : Y
|
||||
out_seg_3[6] : AC23 : output : 2.5 V : : 5A : Y
|
||||
out_seg_3[5] : AC24 : output : 2.5 V : : 5A : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5B :
|
||||
GND : AC26 : gnd : : : :
|
||||
GND : AD1 : : : : B0L :
|
||||
@@ -183,10 +183,10 @@ GND : AD2 : : :
|
||||
GND : AD3 : gnd : : : :
|
||||
GND : AD4 : gnd : : : :
|
||||
AS_DATA1, DATA1 : AD5 : : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
|
||||
out_seg_2[2] : AD6 : output : 2.5 V : : 3A : Y
|
||||
out_seg_2[1] : AD7 : output : 2.5 V : : 3A : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B :
|
||||
VCCIO3B : AD9 : power : : 2.5V : 3B :
|
||||
VCCIO3B : AD9 : power : : 1.2V : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 4A :
|
||||
@@ -196,14 +196,14 @@ VREFB4AN0 : AD15 : power : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD16 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4A :
|
||||
VCCIO4A : AD19 : power : : 2.5V : 4A :
|
||||
VCCIO4A : AD19 : power : : 1.2V : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD23 : : : : 4A :
|
||||
GND : AD24 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 4A :
|
||||
out_seg_1[2] : AD26 : output : 1.2 V : : 4A : Y
|
||||
GND : AE1 : gnd : : : :
|
||||
GND : AE2 : gnd : : : :
|
||||
GXB_NC : AE3 : : : : B0L :
|
||||
@@ -215,21 +215,21 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 4A :
|
||||
VCCIO4A : AE12 : power : : 2.5V : 4A :
|
||||
VCCIO4A : AE12 : power : : 1.2V : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
|
||||
GND : AE17 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
|
||||
HID_Register[4] : AE19 : input : 1.2 V : : 4A : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4A :
|
||||
VCCIO4A : AE22 : power : : 2.5V : 4A :
|
||||
VCCIO4A : AE22 : power : : 1.2V : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 4A :
|
||||
out_seg_1[5] : AE25 : output : 1.2 V : : 4A : Y
|
||||
out_seg_1[4] : AE26 : output : 1.2 V : : 4A : Y
|
||||
GND : AF2 : gnd : : : :
|
||||
GND : AF3 : gnd : : : :
|
||||
GND : AF4 : gnd : : : :
|
||||
@@ -243,7 +243,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A :
|
||||
VCCIO4A : AF15 : power : : 2.5V : 4A :
|
||||
VCCIO4A : AF15 : power : : 1.2V : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
|
||||
@@ -252,7 +252,7 @@ GND : AF20 : gnd : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
|
||||
out_seg_1[7] : AF24 : output : 1.2 V : : 4A : Y
|
||||
GND : AF25 : gnd : : : :
|
||||
RREF : B1 : : : : :
|
||||
GND : B2 : gnd : : : :
|
||||
@@ -312,7 +312,7 @@ GND : D3 : gnd : :
|
||||
GND : D4 : gnd : : : :
|
||||
nCE : D5 : : : : 9A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A :
|
||||
out_seg_1[0] : D7 : output : 2.5 V : : 8A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8A :
|
||||
VCCIO8A : D9 : power : : 2.5V : 8A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 7A :
|
||||
@@ -423,11 +423,11 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : :
|
||||
VCCIO7A : H11 : power : : 2.5V : 7A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7A :
|
||||
out_seg_3[0] : H14 : output : 2.5 V : : 7A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7A :
|
||||
GND : H16 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7A :
|
||||
out_seg_2[0] : H18 : output : 2.5 V : : 7A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6A :
|
||||
VCCIO6A : H21 : power : : 2.5V : 6A :
|
||||
@@ -460,7 +460,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : :
|
||||
VCCPD6A : J22 : power : : 2.5V : 6A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
|
||||
VCCIO6A : J24 : power : : 2.5V : 6A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
|
||||
out_seg_0[0] : J25 : output : 2.5 V : : 6A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
|
||||
GXB_NC : K1 : : : : B1L :
|
||||
GXB_NC : K2 : : : : B1L :
|
||||
@@ -534,7 +534,7 @@ GND : M17 : gnd : :
|
||||
VCC : M18 : power : : 1.1V : :
|
||||
GND : M19 : gnd : : : :
|
||||
VCC : M20 : power : : 1.1V : :
|
||||
clk[0] : M21 : input : 2.5 V : : 6A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
|
||||
VCCIO6A : M23 : power : : 2.5V : 6A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6A :
|
||||
@@ -651,7 +651,7 @@ GND : U4 : gnd : :
|
||||
VCCE_GXBL : U5 : power : : 1.1V : :
|
||||
AS_DATA3, DATA3 : U6 : : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A :
|
||||
VCCIO3B : U8 : power : : 2.5V : 3B :
|
||||
VCCIO3B : U8 : power : : 1.2V : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B :
|
||||
@@ -661,9 +661,9 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4A :
|
||||
VCCIO4A : U18 : power : : 2.5V : 4A :
|
||||
VCCIO4A : U18 : power : : 1.2V : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A :
|
||||
out_seg_2[3] : U20 : output : 2.5 V : : 5A : Y
|
||||
VCCPD5A : U21 : power : : 2.5V : 5A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5A :
|
||||
GND : U23 : gnd : : : :
|
||||
@@ -679,19 +679,19 @@ GND : V6 : : :
|
||||
TDO : V7 : output : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3B :
|
||||
VCCIO3B : V11 : power : : 2.5V : 3B :
|
||||
HID_Register[1] : V10 : input : 1.2 V : : 3B : Y
|
||||
VCCIO3B : V11 : power : : 1.2V : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4A :
|
||||
GND : V16 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V19 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5A :
|
||||
out_seg_0[3] : V17 : output : 1.2 V : : 4A : Y
|
||||
out_seg_0[2] : V18 : output : 1.2 V : : 4A : Y
|
||||
out_seg_0[1] : V19 : output : 1.2 V : : 4A : Y
|
||||
out_seg_2[5] : V20 : output : 2.5 V : : 5A : Y
|
||||
VCCIO5A : V21 : power : : 2.5V : 5A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5A :
|
||||
out_seg_2[4] : V22 : output : 2.5 V : : 5A : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B :
|
||||
@@ -706,17 +706,17 @@ VCCA_FPLL : W7 : power : : 2.5V
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A :
|
||||
GND : W9 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B :
|
||||
HID_PC[0] : W11 : input : 1.2 V : : 3B : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A :
|
||||
VCCIO4A : W14 : power : : 2.5V : 4A :
|
||||
VCCIO4A : W14 : power : : 1.2V : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4A :
|
||||
out_seg_0[4] : W18 : output : 1.2 V : : 4A : Y
|
||||
GND : W19 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A :
|
||||
out_seg_2[7] : W20 : output : 2.5 V : : 5A : Y
|
||||
out_seg_2[6] : W21 : output : 2.5 V : : 5A : Y
|
||||
VCCPGM : W22 : power : : 1.8V/2.5V/3.0V/3.3V : :
|
||||
VREFB5AN0 : W23 : power : : : 5A :
|
||||
VCCIO5B : W24 : power : : 2.5V : 5B :
|
||||
@@ -732,19 +732,19 @@ VCCIO3A : Y7 : power : : 2.5V
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y9 : : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3B :
|
||||
HID_Register[3] : Y11 : input : 1.2 V : : 3B : Y
|
||||
GND : Y12 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A :
|
||||
VCCIO4A : Y17 : power : : 2.5V : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 4A :
|
||||
clk[0] : Y16 : input : 1.2 V : : 4A : Y
|
||||
VCCIO4A : Y17 : power : : 1.2V : 4A :
|
||||
out_seg_0[7] : Y18 : output : 1.2 V : : 4A : Y
|
||||
out_seg_0[6] : Y19 : output : 1.2 V : : 4A : Y
|
||||
out_seg_0[5] : Y20 : output : 1.2 V : : 4A : Y
|
||||
VCCA_FPLL : Y21 : power : : 2.5V : :
|
||||
GND : Y22 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A :
|
||||
out_seg_3[2] : Y23 : output : 2.5 V : : 5A : Y
|
||||
out_seg_3[1] : Y24 : output : 2.5 V : : 5A : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B :
|
||||
Binary file not shown.
@@ -1,5 +1,5 @@
|
||||
Timing Analyzer report for assignment2
|
||||
Tue Oct 13 15:09:06 2026
|
||||
Tue Oct 13 16:19:07 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
@@ -99,7 +99,7 @@ on the Quartus Prime software download page.
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 0.1% ;
|
||||
; Processor 2 ; 0.0% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
@@ -281,48 +281,220 @@ No synchronizer chains to report.
|
||||
+------------------+-------+------+----------+---------+---------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Board Trace Model Assignments ;
|
||||
+-----+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
|
||||
+-----+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Board Trace Model Assignments ;
|
||||
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
|
||||
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||
; out_seg_0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_0[1] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_0[2] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_0[3] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_0[4] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_0[5] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_0[6] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_0[7] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_1[1] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_1[2] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_1[3] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_1[4] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_1[5] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_1[6] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_1[7] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_2[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_2[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_2[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_2[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_2[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_2[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_2[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_2[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_3[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_3[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_3[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_3[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_3[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_3[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_3[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; out_seg_3[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------+
|
||||
; Input Transition Times ;
|
||||
+--------+--------------+-----------------+-----------------+
|
||||
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
|
||||
+--------+--------------+-----------------+-----------------+
|
||||
; clk[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
+--------+--------------+-----------------+-----------------+
|
||||
+--------------------------------------------------------------------+
|
||||
; Input Transition Times ;
|
||||
+-----------------+--------------+-----------------+-----------------+
|
||||
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
|
||||
+-----------------+--------------+-----------------+-----------------+
|
||||
; clk[0] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||
; HID_Register[0] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||
; HID_Register[1] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||
; HID_Register[2] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||
; HID_Register[3] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||
; HID_Register[4] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||
; HID_PC[0] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||
; HID_Hi_Low[0] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||
+-----------------+--------------+-----------------+-----------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
|
||||
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
|
||||
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; out_seg_0[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
|
||||
; out_seg_0[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
|
||||
; out_seg_0[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ;
|
||||
; out_seg_0[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ;
|
||||
; out_seg_0[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
|
||||
; out_seg_0[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ;
|
||||
; out_seg_0[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
|
||||
; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ;
|
||||
; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
|
||||
; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
|
||||
; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
|
||||
; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
|
||||
; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
|
||||
; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
|
||||
; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
|
||||
; out_seg_2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; out_seg_2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; out_seg_2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
|
||||
; out_seg_2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
|
||||
; out_seg_2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
|
||||
; out_seg_2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
|
||||
; out_seg_2[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
|
||||
; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
|
||||
; out_seg_3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; out_seg_3[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; out_seg_3[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; out_seg_3[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; out_seg_3[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; out_seg_3[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; out_seg_3[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
|
||||
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
|
||||
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; out_seg_0[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
|
||||
; out_seg_0[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
|
||||
; out_seg_0[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ;
|
||||
; out_seg_0[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ;
|
||||
; out_seg_0[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
|
||||
; out_seg_0[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ;
|
||||
; out_seg_0[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
|
||||
; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ;
|
||||
; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ;
|
||||
; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ;
|
||||
; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ;
|
||||
; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ;
|
||||
; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ;
|
||||
; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ;
|
||||
; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
|
||||
; out_seg_2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; out_seg_2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; out_seg_2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
|
||||
; out_seg_2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
|
||||
; out_seg_2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
|
||||
; out_seg_2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
|
||||
; out_seg_2[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
|
||||
; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
|
||||
; out_seg_3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; out_seg_3[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; out_seg_3[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; out_seg_3[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; out_seg_3[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; out_seg_3[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; out_seg_3[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
|
||||
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
|
||||
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; out_seg_0[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
|
||||
; out_seg_0[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
|
||||
; out_seg_0[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ;
|
||||
; out_seg_0[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ;
|
||||
; out_seg_0[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
|
||||
; out_seg_0[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ;
|
||||
; out_seg_0[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
|
||||
; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ;
|
||||
; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
|
||||
; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
|
||||
; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
|
||||
; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
|
||||
; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
|
||||
; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
|
||||
; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
|
||||
; out_seg_2[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; out_seg_2[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; out_seg_2[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
|
||||
; out_seg_2[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
|
||||
; out_seg_2[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
|
||||
; out_seg_2[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
|
||||
; out_seg_2[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
|
||||
; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
|
||||
; out_seg_3[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; out_seg_3[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; out_seg_3[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; out_seg_3[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; out_seg_3[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; out_seg_3[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; out_seg_3[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
|
||||
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
|
||||
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; out_seg_0[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
|
||||
; out_seg_0[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
|
||||
; out_seg_0[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ;
|
||||
; out_seg_0[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ;
|
||||
; out_seg_0[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
|
||||
; out_seg_0[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ;
|
||||
; out_seg_0[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
|
||||
; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ;
|
||||
; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
|
||||
; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
|
||||
; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
|
||||
; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
|
||||
; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
|
||||
; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
|
||||
; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
|
||||
; out_seg_2[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; out_seg_2[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; out_seg_2[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
|
||||
; out_seg_2[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
|
||||
; out_seg_2[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
|
||||
; out_seg_2[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
|
||||
; out_seg_2[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
|
||||
; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
|
||||
; out_seg_3[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; out_seg_3[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; out_seg_3[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; out_seg_3[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; out_seg_3[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; out_seg_3[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; out_seg_3[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
-------------------
|
||||
@@ -363,7 +535,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Timing Analyzer
|
||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Info: Processing started: Tue Oct 13 15:09:02 2026
|
||||
Info: Processing started: Tue Oct 13 16:19:02 2026
|
||||
Info: Command: quartus_sta assignment2 -c assignment2
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
@@ -423,9 +595,9 @@ Info (332140): No Minimum Pulse Width paths to report
|
||||
Info (332101): Design is fully constrained for setup requirements
|
||||
Info (332101): Design is fully constrained for hold requirements
|
||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
|
||||
Info: Peak virtual memory: 718 megabytes
|
||||
Info: Processing ended: Tue Oct 13 15:09:06 2026
|
||||
Info: Elapsed time: 00:00:04
|
||||
Info: Total CPU time (on all processors): 00:00:04
|
||||
Info: Peak virtual memory: 757 megabytes
|
||||
Info: Processing ended: Tue Oct 13 16:19:07 2026
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Total CPU time (on all processors): 00:00:06
|
||||
|
||||
|
||||
Reference in new issue
Block a user