diff --git a/Quartus/A1_Q1/db/seven_seg.db_info b/Quartus/A1_Q1/db/seven_seg.db_info index 77bf752..427bd49 100644 --- a/Quartus/A1_Q1/db/seven_seg.db_info +++ b/Quartus/A1_Q1/db/seven_seg.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Version_Index = 604268800 -Creation_Time = Wed Sep 16 09:35:09 2026 +Creation_Time = Tue Oct 13 16:10:56 2026 diff --git a/Quartus/A1_Q1/seven_seg.qws b/Quartus/A1_Q1/seven_seg.qws index 1145b54..547170a 100644 Binary files a/Quartus/A1_Q1/seven_seg.qws and b/Quartus/A1_Q1/seven_seg.qws differ diff --git a/Quartus/A2/assignment2.qsf b/Quartus/A2/assignment2.qsf index 43e3ff2..05876ca 100644 --- a/Quartus/A2/assignment2.qsf +++ b/Quartus/A2/assignment2.qsf @@ -60,4 +60,63 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_AE19 -to HID_Register[4] +set_location_assignment PIN_Y11 -to HID_Register[3] +set_location_assignment PIN_AC10 -to HID_Register[2] +set_location_assignment PIN_V10 -to HID_Register[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_Register[4] +set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_Register[3] +set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_Register[2] +set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_Register[1] +set_location_assignment PIN_AB10 -to HID_Register[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_Register[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_Register +set_location_assignment PIN_W11 -to HID_PC[0] +set_location_assignment PIN_AC8 -to HID_Hi_Low[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_Hi_Low[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to HID_PC[0] +set_location_assignment PIN_Y16 -to clk[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to clk[0] +set_location_assignment PIN_Y18 -to out_seg_0[7] +set_location_assignment PIN_Y19 -to out_seg_0[6] +set_location_assignment PIN_Y20 -to out_seg_0[5] +set_location_assignment PIN_W18 -to out_seg_0[4] +set_location_assignment PIN_V17 -to out_seg_0[3] +set_location_assignment PIN_V18 -to out_seg_0[2] +set_location_assignment PIN_V19 -to out_seg_0[1] +set_location_assignment PIN_AF24 -to out_seg_1[7] +set_location_assignment PIN_AC19 -to out_seg_1[6] +set_location_assignment PIN_AE25 -to out_seg_1[5] +set_location_assignment PIN_AE26 -to out_seg_1[4] +set_location_assignment PIN_AB19 -to out_seg_1[3] +set_location_assignment PIN_AD26 -to out_seg_1[2] +set_location_assignment PIN_AA18 -to out_seg_1[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_0[7] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_0[6] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_0[5] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_0[4] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_0[3] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_0[2] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_0[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[7] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[6] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[5] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[4] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[3] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[2] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[1] +set_location_assignment PIN_AD7 -to out_seg_2[1] +set_location_assignment PIN_W20 -to out_seg_2[7] +set_location_assignment PIN_AD6 -to out_seg_2[2] +set_location_assignment PIN_U20 -to out_seg_2[3] +set_location_assignment PIN_V22 -to out_seg_2[4] +set_location_assignment PIN_V20 -to out_seg_2[5] +set_location_assignment PIN_W21 -to out_seg_2[6] +set_location_assignment PIN_AC22 -to out_seg_3[7] +set_location_assignment PIN_Y24 -to out_seg_3[1] +set_location_assignment PIN_Y23 -to out_seg_3[2] +set_location_assignment PIN_AA23 -to out_seg_3[3] +set_location_assignment PIN_AA22 -to out_seg_3[4] +set_location_assignment PIN_AC24 -to out_seg_3[5] +set_location_assignment PIN_AC23 -to out_seg_3[6] set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Quartus/A2/db/assignment2.(0).cnf.cdb b/Quartus/A2/db/assignment2.(0).cnf.cdb index 86191e5..ed9f812 100644 Binary files a/Quartus/A2/db/assignment2.(0).cnf.cdb and b/Quartus/A2/db/assignment2.(0).cnf.cdb differ diff --git a/Quartus/A2/db/assignment2.(0).cnf.hdb b/Quartus/A2/db/assignment2.(0).cnf.hdb index 8f9dee3..e47187b 100644 Binary files a/Quartus/A2/db/assignment2.(0).cnf.hdb and b/Quartus/A2/db/assignment2.(0).cnf.hdb differ diff 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differ diff --git a/Quartus/A2/db/assignment2.(59).cnf.hdb b/Quartus/A2/db/assignment2.(59).cnf.hdb new file mode 100644 index 0000000..59126f6 Binary files /dev/null and b/Quartus/A2/db/assignment2.(59).cnf.hdb differ diff --git a/Quartus/A2/db/assignment2.asm.qmsg b/Quartus/A2/db/assignment2.asm.qmsg index 6ce33e6..171a2a5 100644 --- a/Quartus/A2/db/assignment2.asm.qmsg +++ b/Quartus/A2/db/assignment2.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791864535759 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791864535759 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 15:08:55 2026 " "Processing started: Tue Oct 13 15:08:55 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791864535759 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1791864535759 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1791864535759 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1791864536401 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1791864540830 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "521 " "Peak virtual memory: 521 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791864541075 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 15:09:01 2026 " "Processing ended: Tue Oct 13 15:09:01 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791864541075 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791864541075 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791864541075 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1791864541075 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791868735615 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791868735616 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:18:55 2026 " "Processing started: Tue Oct 13 16:18:55 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791868735616 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1791868735616 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1791868735616 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1791868736314 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1791868740928 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "508 " "Peak virtual memory: 508 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791868741112 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:19:01 2026 " "Processing ended: Tue Oct 13 16:19:01 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791868741112 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791868741112 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791868741112 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1791868741112 ""} diff --git a/Quartus/A2/db/assignment2.asm.rdb b/Quartus/A2/db/assignment2.asm.rdb index 3ae2ef7..6614f3a 100644 Binary files a/Quartus/A2/db/assignment2.asm.rdb and b/Quartus/A2/db/assignment2.asm.rdb differ diff --git a/Quartus/A2/db/assignment2.cmp.bpm b/Quartus/A2/db/assignment2.cmp.bpm index c7f3f4e..ac707fe 100644 Binary files a/Quartus/A2/db/assignment2.cmp.bpm and b/Quartus/A2/db/assignment2.cmp.bpm differ diff --git a/Quartus/A2/db/assignment2.cmp.cdb b/Quartus/A2/db/assignment2.cmp.cdb index f53a823..0b65a82 100644 Binary files a/Quartus/A2/db/assignment2.cmp.cdb and b/Quartus/A2/db/assignment2.cmp.cdb differ diff --git a/Quartus/A2/db/assignment2.cmp.hdb b/Quartus/A2/db/assignment2.cmp.hdb index d302ddf..fa70b4a 100644 Binary files a/Quartus/A2/db/assignment2.cmp.hdb and b/Quartus/A2/db/assignment2.cmp.hdb differ diff --git a/Quartus/A2/db/assignment2.cmp.idb b/Quartus/A2/db/assignment2.cmp.idb index 22d6cc5..aa52164 100644 Binary files a/Quartus/A2/db/assignment2.cmp.idb and b/Quartus/A2/db/assignment2.cmp.idb differ diff --git a/Quartus/A2/db/assignment2.cmp.logdb b/Quartus/A2/db/assignment2.cmp.logdb index ade96ef..c93191c 100644 --- a/Quartus/A2/db/assignment2.cmp.logdb +++ b/Quartus/A2/db/assignment2.cmp.logdb @@ -1,40 +1,80 @@ v1 IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, -IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, -IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, -IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, -IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,, -IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,, IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, -IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, -IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Outputs with single-ended I/O Standard or Differential I/O Standard assignments found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034, -IO_RULES_MATRIX,Total Pass,0;0;0;0;0;1;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;1;1;0, +IO_RULES_MATRIX,Total Pass,0;36;36;0;0;40;36;0;0;0;0;0;0;32;0;0;0;0;32;0;0;0;0;32;0;40;40;0, IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,Total Inapplicable,1;1;1;1;1;0;1;1;1;1;1;1;1;1;1;1;1;1;1;1;1;1;1;1;1;0;0;1, +IO_RULES_MATRIX,Total Inapplicable,40;4;4;40;40;0;4;40;40;40;40;40;40;8;40;40;40;40;8;40;40;40;40;8;40;0;0;40, IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,clk[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,clk[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,HID_Register[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,HID_Register[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,HID_Register[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,HID_Register[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,HID_Register[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,HID_PC[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,HID_Hi_Low[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_0[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, 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+IO_RULES_MATRIX,out_seg_3[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_3[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_3[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_3[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_3[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_3[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_3[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_SUMMARY,Total I/O Rules,28, -IO_RULES_SUMMARY,Number of I/O Rules Passed,3, +IO_RULES_SUMMARY,Number of I/O Rules Passed,9, IO_RULES_SUMMARY,Number of I/O Rules Failed,0, IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, -IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,25, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,19, diff --git a/Quartus/A2/db/assignment2.cmp.rdb b/Quartus/A2/db/assignment2.cmp.rdb index 7198c6f..3ca3351 100644 Binary files a/Quartus/A2/db/assignment2.cmp.rdb and b/Quartus/A2/db/assignment2.cmp.rdb differ diff --git a/Quartus/A2/db/assignment2.eda.qmsg b/Quartus/A2/db/assignment2.eda.qmsg index 587cf92..6f78e9e 100644 --- a/Quartus/A2/db/assignment2.eda.qmsg +++ b/Quartus/A2/db/assignment2.eda.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791864547964 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791864547964 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 15:09:07 2026 " "Processing started: Tue Oct 13 15:09:07 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791864547964 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1791864547964 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1791864547964 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1791864548683 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "assignment2.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/ simulation " "Generated file assignment2.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1791864548694 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "659 " "Peak virtual memory: 659 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791864548729 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 15:09:08 2026 " "Processing ended: Tue Oct 13 15:09:08 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791864548729 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791864548729 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791864548729 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1791864548729 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791868749469 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791868749469 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:19:09 2026 " "Processing started: Tue Oct 13 16:19:09 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791868749469 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1791868749469 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1791868749469 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1791868750209 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "assignment2.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/ simulation " "Generated file assignment2.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1791868750264 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "670 " "Peak virtual memory: 670 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791868750313 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:19:10 2026 " "Processing ended: Tue Oct 13 16:19:10 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791868750313 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791868750313 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791868750313 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1791868750313 ""} diff --git a/Quartus/A2/db/assignment2.fit.qmsg b/Quartus/A2/db/assignment2.fit.qmsg index c527cb1..e837968 100644 --- a/Quartus/A2/db/assignment2.fit.qmsg +++ b/Quartus/A2/db/assignment2.fit.qmsg @@ -1,44 +1,45 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1791864510249 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1791864510249 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "assignment2 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"assignment2\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1791864510254 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791864510326 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791864510326 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1791864510728 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1791864510761 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1791864510815 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 1 " "No exact pin location assignment(s) for 1 pins of 1 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1791864511067 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1791864517541 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791864517574 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1791864517576 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1791864517576 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1791864517576 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1791864517576 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1791864517577 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1791864517577 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1791864517577 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1791864517577 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1791864517577 ""} -{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791864517586 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1791864523404 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1791864523405 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1791864523405 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1791864523406 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1791864523406 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1791864523407 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1791864523407 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1791864523409 ""} -{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1791864523444 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791864523845 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1791864524106 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1791864524361 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791864524361 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1791864524870 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y24 X10_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36"} { { 12 { 0 ""} 0 24 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1791864530252 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1791864530252 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1791864530413 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1791864530413 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1791864530413 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791864530415 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.06 " "Total time spent on timing analysis during the Fitter is 0.06 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1791864531142 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1791864531179 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1791864531524 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1791864531524 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1791864532008 ""} -{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791864533291 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1336 " "Peak virtual memory: 1336 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791864534048 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 15:08:54 2026 " "Processing ended: Tue Oct 13 15:08:54 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791864534048 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:25 " "Elapsed time: 00:00:25" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791864534048 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:36 " "Total CPU time (on all processors): 00:00:36" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791864534048 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1791864534048 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1791868704138 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1791868704138 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "assignment2 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"assignment2\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1791868704143 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791868704223 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791868704223 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1791868704647 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1791868704678 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1791868704740 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "4 40 " "No exact pin location assignment(s) for 4 pins of 40 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1791868705016 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1791868711846 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791868711948 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1791868711950 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1791868711950 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1791868711951 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1791868711951 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1791868711951 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1791868711952 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1791868711952 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1791868711952 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1791868711952 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791868711988 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1791868718247 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1791868718248 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1791868718248 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1791868718249 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1791868718250 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1791868718250 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1791868718250 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1791868718253 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1791868718361 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791868718828 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1791868719237 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1791868719488 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791868719488 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1791868720212 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y24 X10_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36"} { { 12 { 0 ""} 0 24 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1791868726720 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1791868726720 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1791868726886 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1791868726886 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1791868726886 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791868726888 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.06 " "Total time spent on timing analysis during the Fitter is 0.06 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1791868728510 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1791868728549 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1791868728999 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1791868728999 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1791868729690 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:05 " "Fitter post-fit operations ending: elapsed time is 00:00:05" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791868733059 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1791868733343 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1337 " "Peak virtual memory: 1337 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791868733957 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:18:53 2026 " "Processing ended: Tue Oct 13 16:18:53 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791868733957 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791868733957 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:42 " "Total CPU time (on all processors): 00:00:42" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791868733957 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1791868733957 ""} diff --git a/Quartus/A2/db/assignment2.hier_info b/Quartus/A2/db/assignment2.hier_info index 522df96..92ee5fd 100644 --- a/Quartus/A2/db/assignment2.hier_info +++ b/Quartus/A2/db/assignment2.hier_info @@ -1,5 +1,44 @@ |assignment2 clk[0] => clk[0].IN2 +HID_Register[0] => ~NO_FANOUT~ +HID_Register[1] => ~NO_FANOUT~ +HID_Register[2] => ~NO_FANOUT~ +HID_Register[3] => ~NO_FANOUT~ +HID_Register[4] => ~NO_FANOUT~ +HID_PC[0] => ~NO_FANOUT~ +HID_Hi_Low[0] => ~NO_FANOUT~ +out_seg_0[0] << seven_seg_4digit:display.segments0 +out_seg_0[1] << seven_seg_4digit:display.segments0 +out_seg_0[2] << seven_seg_4digit:display.segments0 +out_seg_0[3] << seven_seg_4digit:display.segments0 +out_seg_0[4] << seven_seg_4digit:display.segments0 +out_seg_0[5] << seven_seg_4digit:display.segments0 +out_seg_0[6] << seven_seg_4digit:display.segments0 +out_seg_0[7] << seven_seg_4digit:display.segments0 +out_seg_1[0] << seven_seg_4digit:display.segments1 +out_seg_1[1] << seven_seg_4digit:display.segments1 +out_seg_1[2] << seven_seg_4digit:display.segments1 +out_seg_1[3] << seven_seg_4digit:display.segments1 +out_seg_1[4] << seven_seg_4digit:display.segments1 +out_seg_1[5] << seven_seg_4digit:display.segments1 +out_seg_1[6] << seven_seg_4digit:display.segments1 +out_seg_1[7] << seven_seg_4digit:display.segments1 +out_seg_2[0] << seven_seg_4digit:display.segments2 +out_seg_2[1] << seven_seg_4digit:display.segments2 +out_seg_2[2] << seven_seg_4digit:display.segments2 +out_seg_2[3] << seven_seg_4digit:display.segments2 +out_seg_2[4] << seven_seg_4digit:display.segments2 +out_seg_2[5] << seven_seg_4digit:display.segments2 +out_seg_2[6] << seven_seg_4digit:display.segments2 +out_seg_2[7] << seven_seg_4digit:display.segments2 +out_seg_3[0] << seven_seg_4digit:display.segments3 +out_seg_3[1] << seven_seg_4digit:display.segments3 +out_seg_3[2] << seven_seg_4digit:display.segments3 +out_seg_3[3] << seven_seg_4digit:display.segments3 +out_seg_3[4] << seven_seg_4digit:display.segments3 +out_seg_3[5] << seven_seg_4digit:display.segments3 +out_seg_3[6] << seven_seg_4digit:display.segments3 +out_seg_3[7] << seven_seg_4digit:display.segments3 |assignment2|instruction_counter:PC @@ -1552,3 +1591,238 @@ OUT_1[30] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE OUT_1[31] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE +|assignment2|seven_seg_4digit:display +num[0] => num[0].IN1 +num[1] => num[1].IN1 +num[2] => num[2].IN1 +num[3] => num[3].IN1 +num[4] => num[4].IN1 +num[5] => num[5].IN1 +num[6] => num[6].IN1 +num[7] => num[7].IN1 +num[8] => num[8].IN1 +num[9] => num[9].IN1 +num[10] => num[10].IN1 +num[11] => num[11].IN1 +num[12] => num[12].IN1 +num[13] => num[13].IN1 +num[14] => num[14].IN1 +num[15] => num[15].IN1 +segments0[0] <= seven_seg:digit0.segments +segments0[1] <= seven_seg:digit0.segments +segments0[2] <= seven_seg:digit0.segments +segments0[3] <= seven_seg:digit0.segments +segments0[4] <= seven_seg:digit0.segments +segments0[5] <= seven_seg:digit0.segments +segments0[6] <= seven_seg:digit0.segments +segments0[7] <= seven_seg:digit0.segments +segments1[0] <= seven_seg:digit1.segments +segments1[1] <= seven_seg:digit1.segments +segments1[2] <= seven_seg:digit1.segments +segments1[3] <= seven_seg:digit1.segments +segments1[4] <= seven_seg:digit1.segments +segments1[5] <= seven_seg:digit1.segments +segments1[6] <= seven_seg:digit1.segments +segments1[7] <= seven_seg:digit1.segments +segments2[0] <= seven_seg:digit2.segments +segments2[1] <= seven_seg:digit2.segments +segments2[2] <= seven_seg:digit2.segments +segments2[3] <= seven_seg:digit2.segments +segments2[4] <= seven_seg:digit2.segments +segments2[5] <= seven_seg:digit2.segments +segments2[6] <= seven_seg:digit2.segments +segments2[7] <= seven_seg:digit2.segments +segments3[0] <= seven_seg:digit3.segments +segments3[1] <= seven_seg:digit3.segments +segments3[2] <= seven_seg:digit3.segments +segments3[3] <= seven_seg:digit3.segments +segments3[4] <= seven_seg:digit3.segments +segments3[5] <= seven_seg:digit3.segments +segments3[6] <= seven_seg:digit3.segments +segments3[7] <= seven_seg:digit3.segments + + +|assignment2|seven_seg_4digit:display|seven_seg:digit0 +num[0] => Decoder0.IN3 +num[0] => Mux0.IN19 +num[0] => Mux1.IN19 +num[0] => Mux2.IN19 +num[0] => Mux3.IN19 +num[0] => Mux4.IN19 +num[0] => Mux5.IN19 +num[1] => Decoder0.IN2 +num[1] => Mux0.IN18 +num[1] => Mux1.IN18 +num[1] => Mux2.IN18 +num[1] => Mux3.IN18 +num[1] => Mux4.IN18 +num[1] => Mux5.IN18 +num[2] => Decoder0.IN1 +num[2] => Mux0.IN17 +num[2] => Mux1.IN17 +num[2] => Mux2.IN17 +num[2] => Mux3.IN17 +num[2] => Mux4.IN17 +num[2] => Mux5.IN17 +num[3] => Decoder0.IN0 +num[3] => Mux0.IN16 +num[3] => Mux1.IN16 +num[3] => Mux2.IN16 +num[3] => Mux3.IN16 +num[3] => Mux4.IN16 +num[3] => Mux5.IN16 +rbi_inv[0] => Mux0.IN15 +rbi_inv[0] => Mux1.IN15 +rbi_inv[0] => Mux2.IN15 +rbi_inv[0] => Mux3.IN15 +rbi_inv[0] => Mux4.IN15 +rbi_inv[0] => Mux5.IN15 +rbi_inv[0] => segments.DATAB +segments[0] <= segments.DB_MAX_OUTPUT_PORT_TYPE +segments[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE +segments[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE +segments[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE +segments[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE +segments[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +segments[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE +segments[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE + + +|assignment2|seven_seg_4digit:display|seven_seg:digit1 +num[0] => Decoder0.IN3 +num[0] => Mux0.IN19 +num[0] => Mux1.IN19 +num[0] => Mux2.IN19 +num[0] => Mux3.IN19 +num[0] => Mux4.IN19 +num[0] => Mux5.IN19 +num[1] => Decoder0.IN2 +num[1] => Mux0.IN18 +num[1] => Mux1.IN18 +num[1] => Mux2.IN18 +num[1] => Mux3.IN18 +num[1] => Mux4.IN18 +num[1] => Mux5.IN18 +num[2] => Decoder0.IN1 +num[2] => Mux0.IN17 +num[2] => Mux1.IN17 +num[2] => Mux2.IN17 +num[2] => Mux3.IN17 +num[2] => Mux4.IN17 +num[2] => Mux5.IN17 +num[3] => Decoder0.IN0 +num[3] => Mux0.IN16 +num[3] => Mux1.IN16 +num[3] => Mux2.IN16 +num[3] => Mux3.IN16 +num[3] => Mux4.IN16 +num[3] => Mux5.IN16 +rbi_inv[0] => Mux0.IN15 +rbi_inv[0] => Mux1.IN15 +rbi_inv[0] => Mux2.IN15 +rbi_inv[0] => Mux3.IN15 +rbi_inv[0] => Mux4.IN15 +rbi_inv[0] => Mux5.IN15 +rbi_inv[0] => segments.DATAB +segments[0] <= segments.DB_MAX_OUTPUT_PORT_TYPE +segments[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE +segments[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE +segments[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE +segments[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE +segments[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +segments[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE +segments[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE + + +|assignment2|seven_seg_4digit:display|seven_seg:digit2 +num[0] => Decoder0.IN3 +num[0] => Mux0.IN19 +num[0] => Mux1.IN19 +num[0] => Mux2.IN19 +num[0] => Mux3.IN19 +num[0] => Mux4.IN19 +num[0] => Mux5.IN19 +num[1] => Decoder0.IN2 +num[1] => Mux0.IN18 +num[1] => Mux1.IN18 +num[1] => Mux2.IN18 +num[1] => Mux3.IN18 +num[1] => Mux4.IN18 +num[1] => Mux5.IN18 +num[2] => Decoder0.IN1 +num[2] => Mux0.IN17 +num[2] => Mux1.IN17 +num[2] => Mux2.IN17 +num[2] => Mux3.IN17 +num[2] => Mux4.IN17 +num[2] => Mux5.IN17 +num[3] => Decoder0.IN0 +num[3] => Mux0.IN16 +num[3] => Mux1.IN16 +num[3] => Mux2.IN16 +num[3] => Mux3.IN16 +num[3] => Mux4.IN16 +num[3] => Mux5.IN16 +rbi_inv[0] => Mux0.IN15 +rbi_inv[0] => Mux1.IN15 +rbi_inv[0] => Mux2.IN15 +rbi_inv[0] => Mux3.IN15 +rbi_inv[0] => Mux4.IN15 +rbi_inv[0] => Mux5.IN15 +rbi_inv[0] => segments.DATAB +segments[0] <= segments.DB_MAX_OUTPUT_PORT_TYPE +segments[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE +segments[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE +segments[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE +segments[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE +segments[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +segments[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE +segments[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE + + +|assignment2|seven_seg_4digit:display|seven_seg:digit3 +num[0] => Decoder0.IN3 +num[0] => Mux0.IN19 +num[0] => Mux1.IN19 +num[0] => Mux2.IN19 +num[0] => Mux3.IN19 +num[0] => Mux4.IN19 +num[0] => Mux5.IN19 +num[1] => Decoder0.IN2 +num[1] => Mux0.IN18 +num[1] => Mux1.IN18 +num[1] => Mux2.IN18 +num[1] => Mux3.IN18 +num[1] => Mux4.IN18 +num[1] => Mux5.IN18 +num[2] => Decoder0.IN1 +num[2] => Mux0.IN17 +num[2] => Mux1.IN17 +num[2] => Mux2.IN17 +num[2] => Mux3.IN17 +num[2] => Mux4.IN17 +num[2] => Mux5.IN17 +num[3] => Decoder0.IN0 +num[3] => Mux0.IN16 +num[3] => Mux1.IN16 +num[3] => Mux2.IN16 +num[3] => Mux3.IN16 +num[3] => Mux4.IN16 +num[3] => Mux5.IN16 +rbi_inv[0] => Mux0.IN15 +rbi_inv[0] => Mux1.IN15 +rbi_inv[0] => Mux2.IN15 +rbi_inv[0] => Mux3.IN15 +rbi_inv[0] => Mux4.IN15 +rbi_inv[0] => Mux5.IN15 +rbi_inv[0] => segments.DATAB +segments[0] <= segments.DB_MAX_OUTPUT_PORT_TYPE +segments[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE +segments[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE +segments[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE +segments[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE +segments[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +segments[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE +segments[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/Quartus/A2/db/assignment2.hif b/Quartus/A2/db/assignment2.hif index 0458485..3e95992 100644 Binary files a/Quartus/A2/db/assignment2.hif and b/Quartus/A2/db/assignment2.hif differ diff --git a/Quartus/A2/db/assignment2.lpc.html b/Quartus/A2/db/assignment2.lpc.html index ebcf221..8459bf3 100644 --- a/Quartus/A2/db/assignment2.lpc.html +++ b/Quartus/A2/db/assignment2.lpc.html @@ -16,6 +16,86 @@ Output only Bidir +display|digit3 +5 +1 +0 +1 +8 +1 +1 +1 +0 +0 +0 +0 +0 + + +display|digit2 +5 +1 +0 +1 +8 +1 +1 +1 +0 +0 +0 +0 +0 + + +display|digit1 +5 +1 +0 +1 +8 +1 +1 +1 +0 +0 +0 +0 +0 + + +display|digit0 +5 +1 +0 +1 +8 +1 +1 +1 +0 +0 +0 +0 +0 + + +display +16 +16 +0 +16 +32 +16 +16 +16 +0 +0 +0 +0 +0 + + SHIFTER 72 27 diff --git a/Quartus/A2/db/assignment2.lpc.rdb b/Quartus/A2/db/assignment2.lpc.rdb index bf873f2..611a5f3 100644 Binary files a/Quartus/A2/db/assignment2.lpc.rdb and b/Quartus/A2/db/assignment2.lpc.rdb differ diff --git a/Quartus/A2/db/assignment2.lpc.txt b/Quartus/A2/db/assignment2.lpc.txt index 0f52d19..6db1c5f 100644 --- a/Quartus/A2/db/assignment2.lpc.txt +++ b/Quartus/A2/db/assignment2.lpc.txt @@ -3,6 +3,11 @@ +-------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; +-------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; display|digit3 ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; display|digit2 ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; display|digit1 ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; display|digit0 ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; display ; 16 ; 16 ; 0 ; 16 ; 32 ; 16 ; 16 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; SHIFTER ; 72 ; 27 ; 0 ; 27 ; 32 ; 27 ; 27 ; 27 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; ALU|logic_unit ; 66 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; ALU|adder_unit ; 65 ; 0 ; 0 ; 0 ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; diff --git a/Quartus/A2/db/assignment2.map.bpm b/Quartus/A2/db/assignment2.map.bpm index c3dc931..d524dcb 100644 Binary files a/Quartus/A2/db/assignment2.map.bpm and b/Quartus/A2/db/assignment2.map.bpm differ diff --git a/Quartus/A2/db/assignment2.map.cdb b/Quartus/A2/db/assignment2.map.cdb index 6bc7e92..7b7537f 100644 Binary files a/Quartus/A2/db/assignment2.map.cdb and b/Quartus/A2/db/assignment2.map.cdb differ diff --git a/Quartus/A2/db/assignment2.map.hdb b/Quartus/A2/db/assignment2.map.hdb index 8d4db3f..92ca633 100644 Binary files a/Quartus/A2/db/assignment2.map.hdb and b/Quartus/A2/db/assignment2.map.hdb differ diff --git a/Quartus/A2/db/assignment2.map.qmsg b/Quartus/A2/db/assignment2.map.qmsg index 8ae052c..82aada1 100644 --- a/Quartus/A2/db/assignment2.map.qmsg +++ b/Quartus/A2/db/assignment2.map.qmsg @@ -1,32 +1,35 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791864498063 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791864498064 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 15:08:17 2026 " "Processing started: Tue Oct 13 15:08:17 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791864498064 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864498064 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864498064 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791864498375 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791864498375 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 11 11 " "Found 11 design units, including 11 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} { "Info" "ISGN_ENTITY_NAME" "11 assignment2 " "Found entity 11: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791864507414 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864507414 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1791864507550 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rd assignment2.sv(37) " "Verilog HDL or VHDL warning at assignment2.sv(37): object \"rd\" assigned a value but never read" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 37 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1791864507552 "|assignment2"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" { } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 40 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507569 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" { } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507574 ""} -{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1791864507583 "|assignment2|rom:ROM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791864507607 "|assignment2|rom:ROM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791864507607 "|assignment2|rom:ROM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791864507608 "|assignment2|rom:ROM"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier instruction_classifier:INSTRUCTION_CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"instruction_classifier:INSTRUCTION_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 42 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507611 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_module_classifier instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER " "Elaborating entity \"instruction_module_classifier\" for hierarchy \"instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_MODULE_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 43 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507614 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" { } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 49 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507616 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu alu:ALU " "Elaborating entity \"alu\" for hierarchy \"alu:ALU\"" { } { { "../../modules/assignment2.sv" "ALU" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507623 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu alu:ALU\|asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"alu:ALU\|asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507630 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu alu:ALU\|lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"alu:ALU\|lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507635 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shifter shifter:SHIFTER " "Elaborating entity \"shifter\" for hierarchy \"shifter:SHIFTER\"" { } { { "../../modules/assignment2.sv" "SHIFTER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 55 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864507640 ""} -{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507688 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791864507688 ""} -{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507689 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791864507689 ""} -{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507690 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791864507690 ""} -{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507691 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791864507691 ""} -{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 35 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791864507692 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791864507692 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1791864508199 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "32 " "32 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1791864508222 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1791864508337 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864508337 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk\[0\] " "No output dependent on input pin \"clk\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 15 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791864508375 "|assignment2|clk[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1791864508375 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "1 " "Implemented 1 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1791864508375 ""} { "Info" "ICUT_CUT_TM_OPINS" "0 " "Implemented 0 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1791864508375 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1791864508375 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 174 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 174 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "425 " "Peak virtual memory: 425 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791864508386 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 15:08:28 2026 " "Processing ended: Tue Oct 13 15:08:28 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791864508386 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791864508386 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791864508386 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864508386 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791868691584 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791868691585 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:18:11 2026 " "Processing started: Tue Oct 13 16:18:11 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791868691585 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868691585 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868691585 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791868691904 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791868691904 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 13 13 " "Found 13 design units, including 13 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "11 seven_seg " "Found entity 11: seven_seg" { } { { "../../modules/seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "12 seven_seg_4digit " "Found entity 12: seven_seg_4digit" { } { { "../../modules/seven_seg_4digit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} { "Info" "ISGN_ENTITY_NAME" "13 assignment2 " "Found entity 13: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868701292 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868701292 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1791868701433 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rd assignment2.sv(54) " "Verilog HDL or VHDL warning at assignment2.sv(54): object \"rd\" assigned a value but never read" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 54 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1791868701435 "|assignment2"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" { } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 57 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701436 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" { } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 59 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701444 ""} +{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1791868701453 "|assignment2|rom:ROM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791868701487 "|assignment2|rom:ROM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791868701487 "|assignment2|rom:ROM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791868701487 "|assignment2|rom:ROM"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier instruction_classifier:INSTRUCTION_CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"instruction_classifier:INSTRUCTION_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701493 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_module_classifier instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER " "Elaborating entity \"instruction_module_classifier\" for hierarchy \"instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_MODULE_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 68 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701496 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" { } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 74 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701500 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu alu:ALU " "Elaborating entity \"alu\" for hierarchy \"alu:ALU\"" { } { { "../../modules/assignment2.sv" "ALU" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 77 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701508 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu alu:ALU\|asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"alu:ALU\|asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701514 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu alu:ALU\|lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"alu:ALU\|lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701520 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shifter shifter:SHIFTER " "Elaborating entity \"shifter\" for hierarchy \"shifter:SHIFTER\"" { } { { "../../modules/assignment2.sv" "SHIFTER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701526 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg_4digit seven_seg_4digit:display " "Elaborating entity \"seven_seg_4digit\" for hierarchy \"seven_seg_4digit:display\"" { } { { "../../modules/assignment2.sv" "display" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 93 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701531 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg_4digit:display\|seven_seg:digit0 " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg_4digit:display\|seven_seg:digit0\"" { } { { "../../modules/seven_seg_4digit.sv" "digit0" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868701535 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701572 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868701572 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701574 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868701574 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701575 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868701575 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701577 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868701577 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868701579 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868701579 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1791868702092 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[0\] GND " "Pin \"out_seg_0\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[1\] GND " "Pin \"out_seg_0\[1\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[2\] GND " "Pin \"out_seg_0\[2\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[3\] VCC " "Pin \"out_seg_0\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[4\] GND " "Pin \"out_seg_0\[4\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[5\] GND " "Pin \"out_seg_0\[5\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[6\] VCC " "Pin \"out_seg_0\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[7\] GND " "Pin \"out_seg_0\[7\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_0[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[0\] GND " "Pin \"out_seg_1\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[1\] VCC " "Pin \"out_seg_1\[1\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[2\] GND " "Pin \"out_seg_1\[2\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[3\] GND " "Pin \"out_seg_1\[3\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[4\] VCC " "Pin \"out_seg_1\[4\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[5\] VCC " "Pin \"out_seg_1\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[6\] GND " "Pin \"out_seg_1\[6\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[7\] GND " "Pin \"out_seg_1\[7\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_1[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[0\] GND " "Pin \"out_seg_2\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[1\] GND " "Pin \"out_seg_2\[1\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[2\] GND " "Pin \"out_seg_2\[2\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[3\] GND " "Pin \"out_seg_2\[3\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[4\] GND " "Pin \"out_seg_2\[4\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[5\] VCC " "Pin \"out_seg_2\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[6\] VCC " "Pin \"out_seg_2\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[7\] GND " "Pin \"out_seg_2\[7\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_2[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[0\] GND " "Pin \"out_seg_3\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[1\] GND " "Pin \"out_seg_3\[1\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[2\] VCC " "Pin \"out_seg_3\[2\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[3\] VCC " "Pin \"out_seg_3\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[4\] GND " "Pin \"out_seg_3\[4\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[5\] GND " "Pin \"out_seg_3\[5\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[6\] GND " "Pin \"out_seg_3\[6\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[7\] VCC " "Pin \"out_seg_3\[7\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868702109 "|assignment2|out_seg_3[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1791868702109 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "32 " "32 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1791868702113 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1791868702233 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868702233 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk\[0\] " "No output dependent on input pin \"clk\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 16 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|clk[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[0\] " "No output dependent on input pin \"HID_Register\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|HID_Register[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[1\] " "No output dependent on input pin \"HID_Register\[1\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|HID_Register[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[2\] " "No output dependent on input pin \"HID_Register\[2\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|HID_Register[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[3\] " "No output dependent on input pin \"HID_Register\[3\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|HID_Register[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[4\] " "No output dependent on input pin \"HID_Register\[4\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|HID_Register[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_PC\[0\] " "No output dependent on input pin \"HID_PC\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 18 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|HID_PC[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Hi_Low\[0\] " "No output dependent on input pin \"HID_Hi_Low\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868702270 "|assignment2|HID_Hi_Low[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1791868702270 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "40 " "Implemented 40 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1791868702270 ""} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Implemented 32 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1791868702270 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1791868702270 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 214 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 214 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "423 " "Peak virtual memory: 423 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791868702288 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:18:22 2026 " "Processing ended: Tue Oct 13 16:18:22 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791868702288 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791868702288 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791868702288 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868702288 ""} diff --git a/Quartus/A2/db/assignment2.map.rdb b/Quartus/A2/db/assignment2.map.rdb index 35f78e6..a1c4a77 100644 Binary files a/Quartus/A2/db/assignment2.map.rdb and b/Quartus/A2/db/assignment2.map.rdb differ diff --git a/Quartus/A2/db/assignment2.map_bb.cdb b/Quartus/A2/db/assignment2.map_bb.cdb index e46f7b6..d5574fb 100644 Binary files a/Quartus/A2/db/assignment2.map_bb.cdb and b/Quartus/A2/db/assignment2.map_bb.cdb differ diff --git a/Quartus/A2/db/assignment2.map_bb.hdb b/Quartus/A2/db/assignment2.map_bb.hdb index dc331cc..2fd903e 100644 Binary files a/Quartus/A2/db/assignment2.map_bb.hdb and b/Quartus/A2/db/assignment2.map_bb.hdb differ diff --git a/Quartus/A2/db/assignment2.pplq.rdb b/Quartus/A2/db/assignment2.pplq.rdb new file mode 100644 index 0000000..e1f255e Binary files /dev/null and b/Quartus/A2/db/assignment2.pplq.rdb differ diff --git a/Quartus/A2/db/assignment2.pre_map.hdb b/Quartus/A2/db/assignment2.pre_map.hdb index e03a045..934a41c 100644 Binary files a/Quartus/A2/db/assignment2.pre_map.hdb and b/Quartus/A2/db/assignment2.pre_map.hdb differ diff --git a/Quartus/A2/db/assignment2.root_partition.map.reg_db.cdb b/Quartus/A2/db/assignment2.root_partition.map.reg_db.cdb index e3cdaae..b9d1fed 100644 Binary files a/Quartus/A2/db/assignment2.root_partition.map.reg_db.cdb and b/Quartus/A2/db/assignment2.root_partition.map.reg_db.cdb differ diff --git a/Quartus/A2/db/assignment2.rtlv.hdb b/Quartus/A2/db/assignment2.rtlv.hdb index f712678..cba2dcf 100644 Binary files a/Quartus/A2/db/assignment2.rtlv.hdb and b/Quartus/A2/db/assignment2.rtlv.hdb differ diff --git a/Quartus/A2/db/assignment2.rtlv_sg.cdb b/Quartus/A2/db/assignment2.rtlv_sg.cdb index 34dfbc5..86ef8de 100644 Binary files a/Quartus/A2/db/assignment2.rtlv_sg.cdb and b/Quartus/A2/db/assignment2.rtlv_sg.cdb differ diff --git a/Quartus/A2/db/assignment2.rtlv_sg_swap.cdb b/Quartus/A2/db/assignment2.rtlv_sg_swap.cdb index 5640608..679831e 100644 Binary files a/Quartus/A2/db/assignment2.rtlv_sg_swap.cdb and b/Quartus/A2/db/assignment2.rtlv_sg_swap.cdb differ diff --git a/Quartus/A2/db/assignment2.sta.qmsg b/Quartus/A2/db/assignment2.sta.qmsg index c7c2f17..45b5b83 100644 --- a/Quartus/A2/db/assignment2.sta.qmsg +++ b/Quartus/A2/db/assignment2.sta.qmsg @@ -1,61 +1,61 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791864542754 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791864542754 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 15:09:02 2026 " "Processing started: Tue Oct 13 15:09:02 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791864542754 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1791864542754 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta assignment2 -c assignment2 " "Command: quartus_sta assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1791864542755 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1791864542812 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1791864543269 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1791864543269 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791864543339 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791864543339 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1791864543906 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791864543907 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791864543907 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791864543907 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1791864543908 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791864543908 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1791864543908 ""} -{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1791864543912 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791864543913 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864543914 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864543918 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864543918 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864543919 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864543920 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864543921 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791864543923 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791864543963 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791864544799 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791864544885 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791864544886 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791864544886 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791864544886 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864544887 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864544889 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864544889 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864544890 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864544891 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864544892 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791864544894 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791864545133 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791864545614 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791864545648 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791864545648 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791864545648 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791864545648 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545649 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545650 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545651 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545652 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545652 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791864545655 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791864545798 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791864545798 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791864545798 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791864545799 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545800 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545801 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545801 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545802 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791864545803 ""} -{ "Info" "ISTA_UCP_CONSTRAINED" "setup " "Design is fully constrained for setup requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791864546312 ""} -{ "Info" "ISTA_UCP_CONSTRAINED" "hold " "Design is fully constrained for hold requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791864546312 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "718 " "Peak virtual memory: 718 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791864546330 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 15:09:06 2026 " "Processing ended: Tue Oct 13 15:09:06 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791864546330 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791864546330 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791864546330 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1791864546330 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791868742624 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791868742625 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:19:02 2026 " "Processing started: Tue Oct 13 16:19:02 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791868742625 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1791868742625 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta assignment2 -c assignment2 " "Command: quartus_sta assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1791868742625 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1791868742686 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1791868743231 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1791868743231 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791868743317 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791868743317 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1791868743927 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791868743927 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791868743927 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791868743928 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1791868743928 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791868743928 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1791868743929 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1791868743934 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791868743935 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868743936 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868743939 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868743940 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868743941 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868743942 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868743942 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791868743945 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791868743995 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791868745087 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791868745180 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791868745180 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791868745181 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791868745181 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868745181 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868745183 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868745184 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868745185 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868745185 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868745186 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791868745188 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791868745441 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791868746020 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791868746061 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791868746061 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791868746061 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791868746062 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746063 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746063 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746064 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746065 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746066 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791868746068 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791868746215 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791868746215 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791868746215 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791868746215 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746216 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746217 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746218 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746219 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791868746219 ""} +{ "Info" "ISTA_UCP_CONSTRAINED" "setup " "Design is fully constrained for setup requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791868747876 ""} +{ "Info" "ISTA_UCP_CONSTRAINED" "hold " "Design is fully constrained for hold requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791868747876 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "757 " "Peak virtual memory: 757 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791868747905 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:19:07 2026 " "Processing ended: Tue Oct 13 16:19:07 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791868747905 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791868747905 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791868747905 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1791868747905 ""} diff --git a/Quartus/A2/db/assignment2.sta.rdb b/Quartus/A2/db/assignment2.sta.rdb index 5ecbfed..7a3b4ed 100644 Binary files a/Quartus/A2/db/assignment2.sta.rdb and b/Quartus/A2/db/assignment2.sta.rdb differ diff --git a/Quartus/A2/db/assignment2.sta_cmp.7_H6_slow_1100mv_85c.tdb b/Quartus/A2/db/assignment2.sta_cmp.7_H6_slow_1100mv_85c.tdb index f3ae18d..1d958f9 100644 Binary files a/Quartus/A2/db/assignment2.sta_cmp.7_H6_slow_1100mv_85c.tdb and b/Quartus/A2/db/assignment2.sta_cmp.7_H6_slow_1100mv_85c.tdb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_0c.ddb b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_0c.ddb index aba38c0..3e6a483 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_0c.ddb and b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_0c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_85c.ddb b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_85c.ddb index d8030c2..c160595 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_85c.ddb and b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_85c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_0c.ddb b/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_0c.ddb index 479718e..6f0c000 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_0c.ddb and b/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_0c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_85c.ddb b/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_85c.ddb index 7d048ee..35dcd02 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_85c.ddb and b/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_85c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_0c.ddb b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_0c.ddb index 2d98789..f96ec8c 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_0c.ddb and b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_0c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_85c.ddb b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_85c.ddb index 7c127f4..412a9a3 100644 Binary files a/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_85c.ddb and b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_85c.ddb differ diff --git a/Quartus/A2/db/assignment2.tmw_info b/Quartus/A2/db/assignment2.tmw_info index 4a8ea6c..ae8044d 100644 --- a/Quartus/A2/db/assignment2.tmw_info +++ b/Quartus/A2/db/assignment2.tmw_info @@ -1,7 +1,7 @@ -start_full_compilation:s:00:00:52 +start_full_compilation:s:00:01:00 start_analysis_synthesis:s:00:00:12-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:25-start_full_compilation +start_fitter:s:00:00:32-start_full_compilation start_assembler:s:00:00:07-start_full_compilation -start_timing_analyzer:s:00:00:06-start_full_compilation +start_timing_analyzer:s:00:00:07-start_full_compilation start_eda_netlist_writer:s:00:00:02-start_full_compilation diff --git a/Quartus/A2/db/assignment2.vpr.ammdb b/Quartus/A2/db/assignment2.vpr.ammdb index 5a53bbf..fa8be6a 100644 Binary files a/Quartus/A2/db/assignment2.vpr.ammdb and b/Quartus/A2/db/assignment2.vpr.ammdb differ diff --git a/Quartus/A2/db/prev_cmp_assignment2.qmsg b/Quartus/A2/db/prev_cmp_assignment2.qmsg index 1e094f6..8596cc3 100644 --- a/Quartus/A2/db/prev_cmp_assignment2.qmsg +++ b/Quartus/A2/db/prev_cmp_assignment2.qmsg @@ -1,17 +1,57 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791864437215 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791864437215 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 15:07:17 2026 " "Processing started: Tue Oct 13 15:07:17 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791864437215 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864437215 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864437215 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791864437534 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791864437534 ""} -{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../rom.sv assignment2.sv(5) " "Verilog HDL File I/O error at assignment2.sv(5): can't open Verilog Design File \"../../rom.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 5 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446822 ""} -{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../ram.sv assignment2.sv(6) " "Verilog HDL File I/O error at assignment2.sv(6): can't open Verilog Design File \"../../ram.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 6 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446823 ""} -{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../register_file.sv assignment2.sv(7) " "Verilog HDL File I/O error at assignment2.sv(7): can't open Verilog Design File \"../../register_file.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 7 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446823 ""} -{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../instruction_counter.sv assignment2.sv(8) " "Verilog HDL File I/O error at assignment2.sv(8): can't open Verilog Design File \"../../instruction_counter.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 8 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446823 ""} -{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../instruction_classifier.sv assignment2.sv(9) " "Verilog HDL File I/O error at assignment2.sv(9): can't open Verilog Design File \"../../instruction_classifier.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 9 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446824 ""} -{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../instruction_module_classifier.sv assignment2.sv(10) " "Verilog HDL File I/O error at assignment2.sv(10): can't open Verilog Design File \"../../instruction_module_classifier.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 10 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446824 ""} -{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../alu.sv assignment2.sv(11) " "Verilog HDL File I/O error at assignment2.sv(11): can't open Verilog Design File \"../../alu.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 11 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446825 ""} -{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../shifter.sv assignment2.sv(12) " "Verilog HDL File I/O error at assignment2.sv(12): can't open Verilog Design File \"../../shifter.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 12 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446825 ""} -{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "assignment2 assignment2.sv(26) " "Ignored design unit \"assignment2\" at assignment2.sv(26) due to previous errors" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791864446825 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864446826 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 9 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 9 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "403 " "Peak virtual memory: 403 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791864446879 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 13 15:07:26 2026 " "Processing ended: Tue Oct 13 15:07:26 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791864446879 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791864446879 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791864446879 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864446879 ""} -{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 11 s 1 " "Quartus Prime Full Compilation was unsuccessful. 11 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864447553 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791868619871 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791868619871 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:16:59 2026 " "Processing started: Tue Oct 13 16:16:59 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791868619871 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868619871 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868619871 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791868620205 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791868620205 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 13 13 " "Found 13 design units, including 13 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "11 seven_seg " "Found entity 11: seven_seg" { } { { "../../modules/seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "12 seven_seg_4digit " "Found entity 12: seven_seg_4digit" { } { { "../../modules/seven_seg_4digit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} { "Info" "ISGN_ENTITY_NAME" "13 assignment2 " "Found entity 13: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791868629731 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868629731 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1791868629879 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rd assignment2.sv(54) " "Verilog HDL or VHDL warning at assignment2.sv(54): object \"rd\" assigned a value but never read" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 54 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1791868629882 "|assignment2"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" { } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 57 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629883 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" { } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 59 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629891 ""} +{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1791868629900 "|assignment2|rom:ROM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791868629925 "|assignment2|rom:ROM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791868629925 "|assignment2|rom:ROM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791868629925 "|assignment2|rom:ROM"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier instruction_classifier:INSTRUCTION_CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"instruction_classifier:INSTRUCTION_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629929 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_module_classifier instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER " "Elaborating entity \"instruction_module_classifier\" for hierarchy \"instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_MODULE_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 68 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629932 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" { } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 74 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629934 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu alu:ALU " "Elaborating entity \"alu\" for hierarchy \"alu:ALU\"" { } { { "../../modules/assignment2.sv" "ALU" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 77 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629941 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu alu:ALU\|asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"alu:ALU\|asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629947 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu alu:ALU\|lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"alu:ALU\|lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629953 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shifter shifter:SHIFTER " "Elaborating entity \"shifter\" for hierarchy \"shifter:SHIFTER\"" { } { { "../../modules/assignment2.sv" "SHIFTER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629959 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg_4digit seven_seg_4digit:display " "Elaborating entity \"seven_seg_4digit\" for hierarchy \"seven_seg_4digit:display\"" { } { { "../../modules/assignment2.sv" "display" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 93 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629964 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg_4digit:display\|seven_seg:digit0 " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg_4digit:display\|seven_seg:digit0\"" { } { { "../../modules/seven_seg_4digit.sv" "digit0" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868629967 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630011 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868630011 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630012 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868630012 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630013 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868630013 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630014 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868630014 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791868630015 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791868630015 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1791868630532 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[0\] GND " "Pin \"out_seg_0\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[1\] GND " "Pin \"out_seg_0\[1\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[2\] GND " "Pin \"out_seg_0\[2\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[3\] VCC " "Pin \"out_seg_0\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[4\] GND " "Pin \"out_seg_0\[4\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[5\] GND " "Pin \"out_seg_0\[5\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[6\] VCC " "Pin \"out_seg_0\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[7\] GND " "Pin \"out_seg_0\[7\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_0[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[0\] GND " "Pin \"out_seg_1\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[1\] VCC " "Pin \"out_seg_1\[1\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[2\] GND " "Pin \"out_seg_1\[2\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[3\] GND " "Pin \"out_seg_1\[3\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[4\] VCC " "Pin \"out_seg_1\[4\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[5\] VCC " "Pin \"out_seg_1\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[6\] GND " "Pin \"out_seg_1\[6\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[7\] GND " "Pin \"out_seg_1\[7\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_1[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[0\] GND " "Pin \"out_seg_2\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[1\] GND " "Pin \"out_seg_2\[1\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[2\] GND " "Pin \"out_seg_2\[2\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[3\] GND " "Pin \"out_seg_2\[3\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[4\] GND " "Pin \"out_seg_2\[4\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[5\] VCC " "Pin \"out_seg_2\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[6\] VCC " "Pin \"out_seg_2\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[7\] GND " "Pin \"out_seg_2\[7\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_2[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[0\] GND " "Pin \"out_seg_3\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[1\] GND " "Pin \"out_seg_3\[1\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[2\] VCC " "Pin \"out_seg_3\[2\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[3\] VCC " "Pin \"out_seg_3\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[4\] GND " "Pin \"out_seg_3\[4\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[5\] GND " "Pin \"out_seg_3\[5\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[6\] GND " "Pin \"out_seg_3\[6\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[7\] VCC " "Pin \"out_seg_3\[7\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1791868630549 "|assignment2|out_seg_3[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1791868630549 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "32 " "32 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1791868630553 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1791868630688 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791868630688 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk\[0\] " "No output dependent on input pin \"clk\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 16 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|clk[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[0\] " "No output dependent on input pin \"HID_Register\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|HID_Register[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[1\] " "No output dependent on input pin \"HID_Register\[1\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|HID_Register[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[2\] " "No output dependent on input pin \"HID_Register\[2\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|HID_Register[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[3\] " "No output dependent on input pin \"HID_Register\[3\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|HID_Register[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[4\] " "No output dependent on input pin \"HID_Register\[4\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|HID_Register[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_PC\[0\] " "No output dependent on input pin \"HID_PC\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 18 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|HID_PC[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Hi_Low\[0\] " "No output dependent on input pin \"HID_Hi_Low\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791868630724 "|assignment2|HID_Hi_Low[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1791868630724 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "40 " "Implemented 40 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1791868630724 ""} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Implemented 32 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1791868630724 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1791868630724 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 214 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 214 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "428 " "Peak virtual memory: 428 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791868630737 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 16:17:10 2026 " "Processing ended: Tue Oct 13 16:17:10 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791868630737 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791868630737 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791868630737 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791868630737 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1791868632250 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791868632250 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:17:11 2026 " "Processing started: Tue Oct 13 16:17:11 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791868632250 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1791868632250 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1791868632250 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1791868632306 ""} +{ "Info" "0" "" "Project = assignment2" { } { } 0 0 "Project = assignment2" 0 0 "Fitter" 0 0 1791868632307 ""} +{ "Info" "0" "" "Revision = assignment2" { } { } 0 0 "Revision = assignment2" 0 0 "Fitter" 0 0 1791868632307 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1791868632503 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1791868632503 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "assignment2 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"assignment2\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1791868632508 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791868632575 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791868632575 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1791868632996 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1791868633024 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1791868633075 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "4 40 " "No exact pin location assignment(s) for 4 pins of 40 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1791868633333 ""} +{ "Error" "EFIOMGR_IO_BANK_OUTPUTS_VCCIO_INCOMPATIBLE" "out_seg_2\[7\] 5A 3.3-V LVTTL 3.3V 2.5V " "Pin out_seg_2\[7\] with I/O standard assignment 3.3-V LVTTL is incompatible with I/O bank 5A. I/O standard 3.3-V LVTTL, has a VCCIO requirement of 3.3V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 2.5V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[7] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[7\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 56 14177 15141 0 0 "" 0 "" "" } } } } } 0 169026 "Pin %1!s! with I/O standard assignment %3!s! is incompatible with I/O bank %2!s!. I/O standard %3!s!, has a VCCIO requirement of %4!s!, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of %5!s!. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Fitter" 0 -1 1791868633341 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791868633342 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1791868633368 ""} +{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "32 " "Following 32 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[0\] GND " "Pin out_seg_0\[0\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[0] } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 33 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[1\] GND " "Pin out_seg_0\[1\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[1] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_0\[1\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 34 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[2\] GND " "Pin out_seg_0\[2\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[2] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_0\[2\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 35 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[3\] VCC " "Pin out_seg_0\[3\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[3] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_0\[3\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 36 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[4\] GND " "Pin out_seg_0\[4\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[4] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_0\[4\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 37 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[5\] GND " "Pin out_seg_0\[5\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[5] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_0\[5\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 38 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[6\] VCC " "Pin out_seg_0\[6\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[6] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_0\[6\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 39 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_0\[7\] GND " "Pin out_seg_0\[7\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_0[7] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_0\[7\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 40 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[0\] GND " "Pin out_seg_1\[0\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[0] } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 41 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[1\] VCC " "Pin out_seg_1\[1\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[1] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_1\[1\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 42 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[2\] GND " "Pin out_seg_1\[2\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[2] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_1\[2\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 43 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[3\] GND " "Pin out_seg_1\[3\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[3] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_1\[3\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 44 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[4\] VCC " "Pin out_seg_1\[4\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[4] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_1\[4\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 45 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[5\] VCC " "Pin out_seg_1\[5\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[5] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_1\[5\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 46 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[6\] GND " "Pin out_seg_1\[6\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[6] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_1\[6\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 47 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_1\[7\] GND " "Pin out_seg_1\[7\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_1[7] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_1\[7\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 22 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 48 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[0\] GND " "Pin out_seg_2\[0\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[0] } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 49 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[1\] GND " "Pin out_seg_2\[1\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[1] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[1\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 50 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[2\] GND " "Pin out_seg_2\[2\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[2] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[2\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 51 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[3\] GND " "Pin out_seg_2\[3\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[3] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[3\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 52 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[4\] GND " "Pin out_seg_2\[4\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[4] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[4\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 53 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[5\] VCC " "Pin out_seg_2\[5\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[5] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[5\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 54 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[6\] VCC " "Pin out_seg_2\[6\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[6] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[6\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 55 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_2\[7\] GND " "Pin out_seg_2\[7\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_2[7] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_2\[7\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 56 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[0\] GND " "Pin out_seg_3\[0\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[0] } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 57 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[1\] GND " "Pin out_seg_3\[1\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[1] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_3\[1\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 58 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[2\] VCC " "Pin out_seg_3\[2\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[2] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_3\[2\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 59 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[3\] VCC " "Pin out_seg_3\[3\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[3] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_3\[3\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 60 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[4\] GND " "Pin out_seg_3\[4\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[4] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_3\[4\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 61 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[5\] GND " "Pin out_seg_3\[5\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[5] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_3\[5\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 62 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[6\] GND " "Pin out_seg_3\[6\] has GND driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[6] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_3\[6\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 63 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out_seg_3\[7\] VCC " "Pin out_seg_3\[7\] has VCC driving its datain port" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/oliver/altera_lite/25.1std/quartus/linux64/pin_planner.ppl" { out_seg_3[7] } } } { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "out_seg_3\[7\]" } } } } { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 0 0 } } { "temporary_test_loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 0 { 0 ""} 0 64 14177 15141 0 0 "" 0 "" "" } } } } } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Design Software" 0 -1 1791868633370 ""} } { } 0 169069 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1791868633370 ""} +{ "Error" "EFSV_FITCC_FAIL" "" "Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { } 0 11802 "Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Fitter" 0 -1 1791868633372 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Fitter 2 s 6 s Quartus Prime " "Quartus Prime Fitter was unsuccessful. 2 errors, 6 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "514 " "Peak virtual memory: 514 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791868633478 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 13 16:17:13 2026 " "Processing ended: Tue Oct 13 16:17:13 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791868633478 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791868633478 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791868633478 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1791868633478 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 220 s " "Quartus Prime Full Compilation was unsuccessful. 4 errors, 220 warnings" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1791868634102 ""} diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.ammdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.ammdb index 01edc23..475b3b0 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.ammdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.ammdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb index 41bffe8..4b00f12 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.cdb index 0a69647..4efd65e 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.cdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.cdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.hdb index 61098ab..2d041fa 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.hdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hdb index b1c9440..edf3be1 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.rcfdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.rcfdb index 027d974..6c1ca60 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.rcfdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.rcfdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb index f84dee7..ebf05aa 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi index 2fde693..17630fb 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb index deeee0c..4e00665 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb index d6f8de3..3f83162 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb index d26aee1..14196c3 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb index efd1672..3cf1508 100644 Binary files a/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb differ diff --git a/Quartus/A2/output_files/assignment2.asm.rpt b/Quartus/A2/output_files/assignment2.asm.rpt index cd3b961..a28a8da 100644 --- a/Quartus/A2/output_files/assignment2.asm.rpt +++ b/Quartus/A2/output_files/assignment2.asm.rpt @@ -1,5 +1,5 @@ Assembler report for assignment2 -Tue Oct 13 15:09:01 2026 +Tue Oct 13 16:19:01 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -38,7 +38,7 @@ on the Quartus Prime software download page. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Oct 13 15:09:01 2026 ; +; Assembler Status ; Successful - Tue Oct 13 16:19:01 2026 ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; ; Family ; Cyclone V ; @@ -67,8 +67,8 @@ on the Quartus Prime software download page. +----------------+--------------------------+ ; Option ; Setting ; +----------------+--------------------------+ -; JTAG usercode ; 0x0077D665 ; -; Checksum ; 0x0077D665 ; +; JTAG usercode ; 0x00780D54 ; +; Checksum ; 0x00780D54 ; +----------------+--------------------------+ @@ -78,14 +78,14 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Oct 13 15:08:55 2026 + Info: Processing started: Tue Oct 13 16:18:55 2026 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 521 megabytes - Info: Processing ended: Tue Oct 13 15:09:01 2026 + Info: Peak virtual memory: 508 megabytes + Info: Processing ended: Tue Oct 13 16:19:01 2026 Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:05 + Info: Total CPU time (on all processors): 00:00:06 diff --git a/Quartus/A2/output_files/assignment2.done b/Quartus/A2/output_files/assignment2.done index b148955..35dfb65 100644 --- a/Quartus/A2/output_files/assignment2.done +++ b/Quartus/A2/output_files/assignment2.done @@ -1 +1 @@ -Tue Oct 13 15:09:09 2026 +Tue Oct 13 16:19:11 2026 diff --git a/Quartus/A2/output_files/assignment2.eda.rpt b/Quartus/A2/output_files/assignment2.eda.rpt index e0c1efb..4f23f94 100644 --- a/Quartus/A2/output_files/assignment2.eda.rpt +++ b/Quartus/A2/output_files/assignment2.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for assignment2 -Tue Oct 13 15:09:08 2026 +Tue Oct 13 16:19:10 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -37,7 +37,7 @@ on the Quartus Prime software download page. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Tue Oct 13 15:09:08 2026 ; +; EDA Netlist Writer Status ; Successful - Tue Oct 13 16:19:10 2026 ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; ; Family ; Cyclone V ; @@ -81,13 +81,13 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Oct 13 15:09:07 2026 + Info: Processing started: Tue Oct 13 16:19:09 2026 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file assignment2.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 659 megabytes - Info: Processing ended: Tue Oct 13 15:09:08 2026 + Info: Peak virtual memory: 670 megabytes + Info: Processing ended: Tue Oct 13 16:19:10 2026 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/Quartus/A2/output_files/assignment2.fit.rpt b/Quartus/A2/output_files/assignment2.fit.rpt index 34ccd7b..784149d 100644 --- a/Quartus/A2/output_files/assignment2.fit.rpt +++ b/Quartus/A2/output_files/assignment2.fit.rpt @@ -1,5 +1,5 @@ Fitter report for assignment2 -Tue Oct 13 15:08:53 2026 +Tue Oct 13 16:18:53 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -10,26 +10,28 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition 2. Fitter Summary 3. Fitter Settings 4. Parallel Compilation - 5. Incremental Compilation Preservation Summary - 6. Incremental Compilation Partition Settings - 7. Incremental Compilation Placement Preservation - 8. Pin-Out File - 9. Fitter Resource Usage Summary - 10. Fitter Partition Statistics - 11. Input Pins - 12. I/O Bank Usage - 13. All Package Pins - 14. I/O Assignment Warnings - 15. Fitter Resource Utilization by Entity - 16. Delay Chain Summary - 17. Pad To Core Delay Chain Fanout - 18. Routing Usage Summary - 19. I/O Rules Summary - 20. I/O Rules Details - 21. I/O Rules Matrix - 22. Fitter Device Options - 23. Operating Settings and Conditions - 24. Fitter Messages + 5. Ignored Assignments + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. I/O Assignment Warnings + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Routing Usage Summary + 21. I/O Rules Summary + 22. I/O Rules Details + 23. I/O Rules Matrix + 24. Fitter Device Options + 25. Operating Settings and Conditions + 26. Fitter Messages @@ -56,7 +58,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Tue Oct 13 15:08:53 2026 ; +; Fitter Status ; Successful - Tue Oct 13 16:18:53 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; @@ -65,7 +67,7 @@ on the Quartus Prime software download page. ; Timing Models ; Final ; ; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ; ; Total registers ; 0 ; -; Total pins ; 1 / 364 ( < 1 % ) ; +; Total pins ; 40 / 364 ( 11 % ) ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ; ; Total RAM Blocks ; 0 / 446 ( 0 % ) ; @@ -155,19 +157,28 @@ on the Quartus Prime software download page. +----------------------------+-------------+ -+------------------------------------------------------------------------------------------------+ -; Incremental Compilation Preservation Summary ; -+---------------------+------------------+----------------------------+--------------------------+ -; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; -+---------------------+------------------+----------------------------+--------------------------+ -; Placement (by node) ; ; ; ; -; -- Requested ; 0.00 % ( 0 / 3 ) ; 0.00 % ( 0 / 3 ) ; 0.00 % ( 0 / 3 ) ; -; -- Achieved ; 0.00 % ( 0 / 3 ) ; 0.00 % ( 0 / 3 ) ; 0.00 % ( 0 / 3 ) ; -; ; ; ; ; -; Routing (by net) ; ; ; ; -; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; -; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; -+---------------------+------------------+----------------------------+--------------------------+ ++----------------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++--------------+----------------+--------------+--------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++--------------+----------------+--------------+--------------+---------------+----------------+ +; I/O Standard ; assignment2 ; ; HID_Register ; 1.2 V ; QSF Assignment ; ++--------------+----------------+--------------+--------------+---------------+----------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 81 ) ; 0.00 % ( 0 / 81 ) ; 0.00 % ( 0 / 81 ) ; +; -- Achieved ; 0.00 % ( 0 / 81 ) ; 0.00 % ( 0 / 81 ) ; 0.00 % ( 0 / 81 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -185,7 +196,7 @@ on the Quartus Prime software download page. +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ ; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ -; Top ; 0.00 % ( 0 / 3 ) ; N/A ; Source File ; N/A ; ; +; Top ; 0.00 % ( 0 / 81 ) ; N/A ; Source File ; N/A ; ; ; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ @@ -238,7 +249,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; -- Routing optimization registers ; 0 ; ; ; ; ; ; ; Virtual pins ; 0 ; ; -; I/O pins ; 1 / 364 ; < 1 % ; +; I/O pins ; 40 / 364 ; 11 % ; ; -- Clock pins ; 1 / 14 ; 7 % ; ; -- Dedicated input pins ; 0 / 23 ; 0 % ; ; ; ; ; @@ -273,8 +284,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; Peak interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ; ; Maximum fan-out ; 1 ; ; ; Highest non-global fan-out ; 1 ; ; -; Total fan-out ; 1 ; ; -; Average fan-out ; 0.33 ; ; +; Total fan-out ; 40 ; ; +; Average fan-out ; 0.49 ; ; +-------------------------------------------------------------+--------------------+-------+ @@ -324,7 +335,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; ; ; ; ; ; ; ; ; Virtual pins ; 0 ; 0 ; -; I/O pins ; 1 ; 0 ; +; I/O pins ; 40 ; 0 ; ; I/O registers ; 0 ; 0 ; ; Total block memory bits ; 0 ; 0 ; ; Total block memory implementation bits ; 0 ; 0 ; @@ -336,7 +347,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; -- Registered Output Connections ; 0 ; 0 ; ; ; ; ; ; Internal Connections ; ; ; -; -- Total Connections ; 1 ; 0 ; +; -- Total Connections ; 40 ; 0 ; ; -- Registered Connections ; 0 ; 0 ; ; ; ; ; ; External Connections ; ; ; @@ -344,8 +355,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; -- hard_block:auto_generated_inst ; 0 ; 0 ; ; ; ; ; ; Partition Interface ; ; ; -; -- Input Ports ; 1 ; 0 ; -; -- Output Ports ; 0 ; 0 ; +; -- Input Ports ; 8 ; 0 ; +; -- Output Ports ; 32 ; 0 ; ; -- Bidir Ports ; 0 ; 0 ; ; ; ; ; ; Registered Ports ; ; ; @@ -364,31 +375,78 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu +-------------------------------------------------------------+---------------------+--------------------------------+ -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; -+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ -; clk[0] ; M21 ; 6A ; 68 ; 32 ; 60 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; HID_Hi_Low[0] ; AC8 ; 3B ; 14 ; 0 ; 51 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; HID_PC[0] ; W11 ; 3B ; 10 ; 0 ; 40 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; HID_Register[0] ; AB10 ; 3B ; 12 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; HID_Register[1] ; V10 ; 3B ; 17 ; 0 ; 74 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; HID_Register[2] ; AC10 ; 3B ; 12 ; 0 ; 51 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; HID_Register[3] ; Y11 ; 3B ; 10 ; 0 ; 57 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; HID_Register[4] ; AE19 ; 4A ; 50 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; clk[0] ; Y16 ; 4A ; 46 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; ++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ -+--------------------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+----------------+---------------+--------------+---------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; -+----------+----------------+---------------+--------------+---------------+ -; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; -; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; -; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 3B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 4A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 6A ; 1 / 48 ( 2 % ) ; 2.5V ; -- ; 2.5V ; -; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 8A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -+----------+----------------+---------------+--------------+---------------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; out_seg_0[0] ; J25 ; 6A ; 68 ; 32 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; out_seg_0[1] ; V19 ; 4A ; 66 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_0[2] ; V18 ; 4A ; 64 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_0[3] ; V17 ; 4A ; 64 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_0[4] ; W18 ; 4A ; 66 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_0[5] ; Y20 ; 4A ; 65 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_0[6] ; Y19 ; 4A ; 65 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_0[7] ; Y18 ; 4A ; 62 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_1[0] ; D7 ; 8A ; 17 ; 61 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; out_seg_1[1] ; AA18 ; 4A ; 62 ; 0 ; 57 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_1[2] ; AD26 ; 4A ; 64 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_1[3] ; AB19 ; 4A ; 65 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_1[4] ; AE26 ; 4A ; 64 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_1[5] ; AE25 ; 4A ; 62 ; 0 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_1[6] ; AC19 ; 4A ; 65 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_1[7] ; AF24 ; 4A ; 62 ; 0 ; 91 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_2[0] ; H18 ; 7A ; 64 ; 61 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; out_seg_2[1] ; AD7 ; 3A ; 7 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_2[2] ; AD6 ; 3A ; 7 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_2[3] ; U20 ; 5A ; 68 ; 13 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_2[4] ; V22 ; 5A ; 68 ; 12 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_2[5] ; V20 ; 5A ; 68 ; 10 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_2[6] ; W21 ; 5A ; 68 ; 11 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_2[7] ; W20 ; 5A ; 68 ; 11 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_3[0] ; H14 ; 7A ; 53 ; 61 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; out_seg_3[1] ; Y24 ; 5A ; 68 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_3[2] ; Y23 ; 5A ; 68 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_3[3] ; AA23 ; 5A ; 68 ; 11 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_3[4] ; AA22 ; 5A ; 68 ; 11 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_3[5] ; AC24 ; 5A ; 68 ; 12 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_3[6] ; AC23 ; 5A ; 68 ; 10 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_3[7] ; AC22 ; 5A ; 68 ; 10 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; ++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++----------------------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+---------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; ++----------+------------------+---------------+--------------+---------------+ +; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; 3A ; 2 / 16 ( 13 % ) ; 2.5V ; -- ; 2.5V ; +; 3B ; 6 / 32 ( 19 % ) ; 1.2V ; -- ; 2.5V ; +; 4A ; 16 / 80 ( 20 % ) ; 1.2V ; -- ; 2.5V ; +; 5A ; 12 / 16 ( 75 % ) ; 2.5V ; -- ; 2.5V ; +; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 6A ; 1 / 48 ( 2 % ) ; 2.5V ; -- ; 2.5V ; +; 7A ; 2 / 80 ( 3 % ) ; 2.5V ; -- ; 2.5V ; +; 8A ; 1 / 32 ( 3 % ) ; 2.5V ; -- ; 2.5V ; ++----------+------------------+---------------+--------------+---------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -429,7 +487,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AA7 ; 47 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AA8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AA9 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; -; AA10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA10 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AA11 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AA12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; AA13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; @@ -437,12 +495,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AA15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AA16 ; 113 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AA17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AA18 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; 151 ; 4A ; out_seg_1[1] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AA19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AA20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA20 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AA21 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA22 ; 170 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AA23 ; 172 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 170 ; 5A ; out_seg_3[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AA23 ; 172 ; 5A ; out_seg_3[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; ; AA24 ; 187 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; AA25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AA26 ; 201 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; @@ -455,16 +513,16 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AB7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; AB8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AB9 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AB10 ; 61 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 61 ; 3B ; HID_Register[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AB11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AB12 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB13 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB13 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AB14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AB15 ; 105 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AB16 ; 111 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AB17 ; 129 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AB18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AB19 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 160 ; 4A ; out_seg_1[3] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AB20 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AB21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AB22 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -479,23 +537,23 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AC5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AC6 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AC7 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ; -; AC8 ; 62 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC8 ; 62 ; 3B ; HID_Hi_Low[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AC9 ; 64 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC10 ; 59 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC10 ; 59 ; 3B ; HID_Register[2] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AC11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AC12 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ; ; AC13 ; 102 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AC14 ; 104 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AC15 ; 103 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC16 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AC17 ; 127 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AC18 ; 120 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC19 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC19 ; 158 ; 4A ; out_seg_1[6] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AC20 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AC21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AC22 ; 166 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AC23 ; 168 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AC24 ; 174 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC22 ; 166 ; 5A ; out_seg_3[7] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AC23 ; 168 ; 5A ; out_seg_3[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AC24 ; 174 ; 5A ; out_seg_3[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; ; AC25 ; 193 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AD1 ; 25 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; @@ -503,10 +561,10 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AD3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AD4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AD5 ; 35 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ; -; AD6 ; 51 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD7 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD6 ; 51 ; 3A ; out_seg_2[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AD7 ; 53 ; 3A ; out_seg_2[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; ; AD8 ; 73 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD9 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD9 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AD10 ; 96 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD11 ; 88 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD12 ; 91 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -516,14 +574,14 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AD16 ; 119 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD17 ; 121 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD18 ; 118 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD19 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AD20 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD21 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD22 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD23 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AD25 ; 191 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AD26 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD26 ; 157 ; 4A ; out_seg_1[2] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AE3 ; 22 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; @@ -535,21 +593,21 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AE9 ; 77 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE10 ; 94 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE11 ; 86 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE12 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE12 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AE13 ; 109 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE14 ; 112 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE15 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AE18 ; 117 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE19 ; 125 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE19 ; 125 ; 4A ; HID_Register[4] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AE20 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE21 ; 131 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE22 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AE23 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE24 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE25 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE26 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE25 ; 152 ; 4A ; out_seg_1[5] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; AE26 ; 155 ; 4A ; out_seg_1[4] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AF4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -563,7 +621,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AF12 ; 99 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF13 ; 107 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF14 ; 110 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF15 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AF15 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AF16 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF17 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF18 ; 115 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -572,7 +630,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AF21 ; 128 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF22 ; 126 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF23 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF24 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF24 ; 150 ; 4A ; out_seg_1[7] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AF25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; B1 ; ; ; RREF ; ; ; ; -- ; ; -- ; -- ; ; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -632,7 +690,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; D5 ; 395 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ; ; D6 ; 352 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D7 ; 356 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 356 ; 8A ; out_seg_1[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; D8 ; 372 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; D9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; D10 ; 316 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -743,11 +801,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; H11 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; H12 ; 327 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; H13 ; 297 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H14 ; 295 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 295 ; 7A ; out_seg_3[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; H15 ; 263 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; H16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; H17 ; 273 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H18 ; 271 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H18 ; 271 ; 7A ; out_seg_2[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; H19 ; 250 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; H20 ; 252 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; H21 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; @@ -780,7 +838,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; J22 ; ; 6A ; VCCPD6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; J23 ; 244 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; J24 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; J25 ; 215 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J25 ; 215 ; 6A ; out_seg_0[0] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; ; J26 ; 217 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; K1 ; 2 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; ; K2 ; 3 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; @@ -854,7 +912,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; M18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; ; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; M20 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; -; M21 ; 216 ; 6A ; clk[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M21 ; 216 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; M22 ; 224 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; M23 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; M24 ; 220 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; @@ -971,7 +1029,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; U5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; ; U6 ; 31 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ; ; U7 ; 39 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U8 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; U9 ; 54 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; U10 ; 81 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; U11 ; 79 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -981,9 +1039,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; U15 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; U16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; U17 ; 130 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U18 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; U19 ; 167 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U20 ; 181 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 181 ; 5A ; out_seg_2[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; ; U21 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; U22 ; 177 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; U23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -999,19 +1057,19 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; V7 ; 28 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ; ; V8 ; 41 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; V9 ; 70 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V10 ; 72 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V11 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V10 ; 72 ; 3B ; HID_Register[1] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; V11 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; V12 ; 98 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; V13 ; 92 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; V14 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; V15 ; 124 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V18 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V19 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V20 ; 169 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V17 ; 154 ; 4A ; out_seg_0[3] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; V18 ; 156 ; 4A ; out_seg_0[2] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; V19 ; 164 ; 4A ; out_seg_0[1] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; V20 ; 169 ; 5A ; out_seg_2[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; ; V21 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; V22 ; 175 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 175 ; 5A ; out_seg_2[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; ; V23 ; 183 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; V24 ; 185 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; V25 ; 197 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; @@ -1026,17 +1084,17 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; W8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; W10 ; 69 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W11 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 57 ; 3B ; HID_PC[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; W12 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W14 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W14 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; W15 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W17 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 162 ; 4A ; out_seg_0[4] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W20 ; 171 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W21 ; 173 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 171 ; 5A ; out_seg_2[7] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W21 ; 173 ; 5A ; out_seg_2[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; ; W22 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; ; W23 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ; ; W24 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; @@ -1052,34 +1110,68 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; Y8 ; 49 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y9 ; 44 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y10 ; 67 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y11 ; 55 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 55 ; 3B ; HID_Register[3] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; Y13 ; 95 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y14 ; 89 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y15 ; 116 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y16 ; 114 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; Y18 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y20 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y16 ; 114 ; 4A ; clk[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; Y17 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; Y18 ; 153 ; 4A ; out_seg_0[7] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; Y19 ; 159 ; 4A ; out_seg_0[6] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; Y20 ; 161 ; 4A ; out_seg_0[5] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; Y21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; Y22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y23 ; 178 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y24 ; 180 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y23 ; 178 ; 5A ; out_seg_3[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; Y24 ; 180 ; 5A ; out_seg_3[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; ; Y25 ; 203 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; Y26 ; 205 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ Note: Pin directions (input, output or bidir) are based on device operating in user mode. -+------------------------------------------+ -; I/O Assignment Warnings ; -+----------+-------------------------------+ -; Pin Name ; Reason ; -+----------+-------------------------------+ -; clk[0] ; Incomplete set of assignments ; -; clk[0] ; Missing location assignment ; -+----------+-------------------------------+ ++-----------------------------------------------------+ +; I/O Assignment Warnings ; ++--------------+--------------------------------------+ +; Pin Name ; Reason ; ++--------------+--------------------------------------+ +; out_seg_0[0] ; Incomplete set of assignments ; +; out_seg_0[1] ; Missing drive strength and slew rate ; +; out_seg_0[2] ; Missing drive strength and slew rate ; +; out_seg_0[3] ; Missing drive strength and slew rate ; +; out_seg_0[4] ; Missing drive strength and slew rate ; +; out_seg_0[5] ; Missing drive strength and slew rate ; +; out_seg_0[6] ; Missing drive strength and slew rate ; +; out_seg_0[7] ; Missing drive strength and slew rate ; +; out_seg_1[0] ; Incomplete set of assignments ; +; out_seg_1[1] ; Missing drive strength and slew rate ; +; out_seg_1[2] ; Missing drive strength and slew rate ; +; out_seg_1[3] ; Missing drive strength and slew rate ; +; out_seg_1[4] ; Missing drive strength and slew rate ; +; out_seg_1[5] ; Missing drive strength and slew rate ; +; out_seg_1[6] ; Missing drive strength and slew rate ; +; out_seg_1[7] ; Missing drive strength and slew rate ; +; out_seg_2[0] ; Incomplete set of assignments ; +; out_seg_2[1] ; Incomplete set of assignments ; +; out_seg_2[2] ; Incomplete set of assignments ; +; out_seg_2[3] ; Incomplete set of assignments ; +; out_seg_2[4] ; Incomplete set of assignments ; +; out_seg_2[5] ; Incomplete set of assignments ; +; out_seg_2[6] ; Incomplete set of assignments ; +; out_seg_2[7] ; Incomplete set of assignments ; +; out_seg_3[0] ; Incomplete set of assignments ; +; out_seg_3[1] ; Incomplete set of assignments ; +; out_seg_3[2] ; Incomplete set of assignments ; +; out_seg_3[3] ; Incomplete set of assignments ; +; out_seg_3[4] ; Incomplete set of assignments ; +; out_seg_3[5] ; Incomplete set of assignments ; +; out_seg_3[6] ; Incomplete set of assignments ; +; out_seg_3[7] ; Incomplete set of assignments ; +; out_seg_0[0] ; Missing location assignment ; +; out_seg_1[0] ; Missing location assignment ; +; out_seg_2[0] ; Missing location assignment ; +; out_seg_3[0] ; Missing location assignment ; ++--------------+--------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -1087,18 +1179,57 @@ Note: Pin directions (input, output or bidir) are based on device operating in u +----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ ; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; +----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ -; |assignment2 ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 1 ; 0 ; |assignment2 ; assignment2 ; work ; +; |assignment2 ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 40 ; 0 ; |assignment2 ; assignment2 ; work ; +----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. -+---------------------------------------------------------------------------------------------------------------------+ -; Delay Chain Summary ; -+--------+----------+----+------+------+----+----+-------+--------+------------------------+--------------------------+ -; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; -+--------+----------+----+------+------+----+----+-------+--------+------------------------+--------------------------+ -; clk[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -+--------+----------+----+------+------+----+----+-------+--------+------------------------+--------------------------+ ++--------------------------------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++-----------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; ++-----------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; clk[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HID_Register[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HID_Register[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HID_Register[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HID_Register[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HID_Register[4] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HID_PC[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HID_Hi_Low[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; out_seg_0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_0[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_2[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_2[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_2[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_2[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_2[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_2[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_2[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_3[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_3[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_3[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_3[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_3[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_3[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_3[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_3[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ++-----------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +---------------------------------------------------+ @@ -1107,6 +1238,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Source Pin / Fanout ; Pad To Core Index ; Setting ; +---------------------+-------------------+---------+ ; clk[0] ; ; ; +; HID_Register[0] ; ; ; +; HID_Register[1] ; ; ; +; HID_Register[2] ; ; ; +; HID_Register[3] ; ; ; +; HID_Register[4] ; ; ; +; HID_PC[0] ; ; ; +; HID_Hi_Low[0] ; ; ; +---------------------+-------------------+---------+ @@ -1142,47 +1280,48 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; I/O Rules Statistic ; Total ; +----------------------------------+-------+ ; Total I/O Rules ; 28 ; -; Number of I/O Rules Passed ; 3 ; +; Number of I/O Rules Passed ; 9 ; ; Number of I/O Rules Failed ; 0 ; ; Number of I/O Rules Unchecked ; 0 ; -; Number of I/O Rules Inapplicable ; 25 ; +; Number of I/O Rules Inapplicable ; 19 ; +----------------------------------+-------+ -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; I/O Rules Details ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+-------------------------------------------------------------------------------------------+------+-------------------+ -; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+-------------------------------------------------------------------------------------------+------+-------------------+ -; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; -; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; -; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; -; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; -; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; -; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; -; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; -; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ; -; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; -; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; -; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; -; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; -; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; -; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; -; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; -; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; -; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; -; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; -; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Outputs with single-ended I/O Standard or Differential I/O Standard assignments found. ; I/O ; ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+-------------------------------------------------------------------------------------------+------+-------------------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -1190,11 +1329,50 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ ; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ; +--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ -; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; 0 ; +; Total Pass ; 0 ; 36 ; 36 ; 0 ; 0 ; 40 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 32 ; 0 ; 40 ; 40 ; 0 ; ; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; Total Inapplicable ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 1 ; +; Total Inapplicable ; 40 ; 4 ; 4 ; 40 ; 40 ; 0 ; 4 ; 40 ; 40 ; 40 ; 40 ; 40 ; 40 ; 8 ; 40 ; 40 ; 40 ; 40 ; 8 ; 40 ; 40 ; 40 ; 40 ; 8 ; 40 ; 0 ; 0 ; 40 ; ; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; clk[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; clk[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; HID_Register[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; HID_Register[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; HID_Register[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; HID_Register[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; HID_Register[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; HID_PC[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; HID_Hi_Low[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_0[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_0[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_0[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_0[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_0[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_0[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_0[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_0[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_2[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_2[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_2[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_2[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_2[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_2[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_2[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_2[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_3[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_3[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_3[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_3[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_3[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_3[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_3[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_3[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ @@ -1252,7 +1430,7 @@ Info (21077): High junction temperature is 85 degrees C Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details -Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 1 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. +Critical Warning (169085): No exact pin location assignment(s) for 4 pins of 40 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. Info (184020): Starting Fitter periphery placement operations Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 Info (176233): Starting register packing @@ -1268,7 +1446,7 @@ Info (332154): The derive_clock_uncertainty command did not apply clock uncertai Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. Info (170189): Fitter placement preparation operations beginning Info (14951): The Fitter is using Advanced Physical Optimization. -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 @@ -1284,11 +1462,12 @@ Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:02 -Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 1336 megabytes - Info: Processing ended: Tue Oct 13 15:08:54 2026 - Info: Elapsed time: 00:00:25 - Info: Total CPU time (on all processors): 00:00:36 +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:05 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info: Quartus Prime Fitter was successful. 0 errors, 7 warnings + Info: Peak virtual memory: 1337 megabytes + Info: Processing ended: Tue Oct 13 16:18:53 2026 + Info: Elapsed time: 00:00:30 + Info: Total CPU time (on all processors): 00:00:42 diff --git a/Quartus/A2/output_files/assignment2.fit.summary b/Quartus/A2/output_files/assignment2.fit.summary index ad0b928..1a40484 100644 --- a/Quartus/A2/output_files/assignment2.fit.summary +++ b/Quartus/A2/output_files/assignment2.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Tue Oct 13 15:08:53 2026 +Fitter Status : Successful - Tue Oct 13 16:18:53 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : assignment2 Top-level Entity Name : assignment2 @@ -7,7 +7,7 @@ Device : 5CGXFC5C6F27C7 Timing Models : Final Logic utilization (in ALMs) : 1 / 29,080 ( < 1 % ) Total registers : 0 -Total pins : 1 / 364 ( < 1 % ) +Total pins : 40 / 364 ( 11 % ) Total virtual pins : 0 Total block memory bits : 0 / 4,567,040 ( 0 % ) Total RAM Blocks : 0 / 446 ( 0 % ) diff --git a/Quartus/A2/output_files/assignment2.flow.rpt b/Quartus/A2/output_files/assignment2.flow.rpt index d3dc2f5..96db9f2 100644 --- a/Quartus/A2/output_files/assignment2.flow.rpt +++ b/Quartus/A2/output_files/assignment2.flow.rpt @@ -1,5 +1,5 @@ Flow report for assignment2 -Tue Oct 13 15:09:08 2026 +Tue Oct 13 16:19:10 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -41,7 +41,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Tue Oct 13 15:09:08 2026 ; +; Flow Status ; Successful - Tue Oct 13 16:19:10 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; @@ -50,7 +50,7 @@ on the Quartus Prime software download page. ; Timing Models ; Final ; ; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ; ; Total registers ; 0 ; -; Total pins ; 1 / 364 ( < 1 % ) ; +; Total pins ; 40 / 364 ( 11 % ) ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ; ; Total DSP Blocks ; 0 / 150 ( 0 % ) ; @@ -68,7 +68,7 @@ on the Quartus Prime software download page. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 10/13/2026 15:08:18 ; +; Start date & time ; 10/13/2026 16:18:11 ; ; Main task ; Compilation ; ; Revision Name ; assignment2 ; +-------------------+---------------------+ @@ -79,7 +79,7 @@ on the Quartus Prime software download page. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 117114050183607.179186449807774 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 117114050183607.179186869111054 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -102,12 +102,12 @@ on the Quartus Prime software download page. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 412 MB ; 00:00:24 ; -; Fitter ; 00:00:24 ; 1.0 ; 1336 MB ; 00:00:36 ; -; Assembler ; 00:00:06 ; 1.0 ; 521 MB ; 00:00:05 ; -; Timing Analyzer ; 00:00:04 ; 1.0 ; 718 MB ; 00:00:04 ; -; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 659 MB ; 00:00:01 ; -; Total ; 00:00:46 ; -- ; -- ; 00:01:10 ; +; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 410 MB ; 00:00:25 ; +; Fitter ; 00:00:30 ; 1.0 ; 1337 MB ; 00:00:42 ; +; Assembler ; 00:00:06 ; 1.0 ; 508 MB ; 00:00:06 ; +; Timing Analyzer ; 00:00:05 ; 1.0 ; 757 MB ; 00:00:05 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 670 MB ; 00:00:01 ; +; Total ; 00:00:53 ; -- ; -- ; 00:01:19 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/Quartus/A2/output_files/assignment2.map.rpt b/Quartus/A2/output_files/assignment2.map.rpt index 861d79c..e960287 100644 --- a/Quartus/A2/output_files/assignment2.map.rpt +++ b/Quartus/A2/output_files/assignment2.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for assignment2 -Tue Oct 13 15:08:28 2026 +Tue Oct 13 16:18:22 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -23,15 +23,20 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition 15. Parameter Settings for User Entity Instance: alu:ALU|asu:adder_unit 16. Parameter Settings for User Entity Instance: alu:ALU|lu:logic_unit 17. Parameter Settings for User Entity Instance: shifter:SHIFTER - 18. Port Connectivity Checks: "shifter:SHIFTER" - 19. Port Connectivity Checks: "alu:ALU" - 20. Port Connectivity Checks: "register_file:REGS" - 21. Port Connectivity Checks: "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" - 22. Port Connectivity Checks: "instruction_classifier:INSTRUCTION_CLASSIFIER" - 23. Port Connectivity Checks: "instruction_counter:PC" - 24. Post-Synthesis Netlist Statistics for Top Partition - 25. Elapsed Time Per Partition - 26. Analysis & Synthesis Messages + 18. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit3" + 19. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit2" + 20. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit1" + 21. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit0" + 22. Port Connectivity Checks: "seven_seg_4digit:display" + 23. Port Connectivity Checks: "shifter:SHIFTER" + 24. Port Connectivity Checks: "alu:ALU" + 25. Port Connectivity Checks: "register_file:REGS" + 26. Port Connectivity Checks: "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" + 27. Port Connectivity Checks: "instruction_classifier:INSTRUCTION_CLASSIFIER" + 28. Port Connectivity Checks: "instruction_counter:PC" + 29. Post-Synthesis Netlist Statistics for Top Partition + 30. Elapsed Time Per Partition + 31. Analysis & Synthesis Messages @@ -58,14 +63,14 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +---------------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Oct 13 15:08:28 2026 ; +; Analysis & Synthesis Status ; Successful - Tue Oct 13 16:18:22 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; ; Family ; Cyclone V ; ; Logic utilization (in ALMs) ; N/A ; ; Total registers ; 0 ; -; Total pins ; 1 ; +; Total pins ; 40 ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 0 ; ; Total DSP Blocks ; 0 ; @@ -197,6 +202,8 @@ on the Quartus Prime software download page. ; ../../modules/lu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv ; ; ; ../../modules/alu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv ; ; ; ../../modules/shifter.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv ; ; +; ../../modules/seven_seg.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv ; ; +; ../../modules/seven_seg_4digit.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv ; ; ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt ; yes ; Auto-Found File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt ; ; +----------------------------------------------------------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+ @@ -217,13 +224,13 @@ on the Quartus Prime software download page. ; ; ; ; Dedicated logic registers ; 0 ; ; ; ; -; I/O pins ; 1 ; +; I/O pins ; 40 ; ; ; ; ; Total DSP Blocks ; 0 ; ; ; ; ; Maximum fan-out node ; clk[0] ; ; Maximum fan-out ; 1 ; -; Total fan-out ; 1 ; +; Total fan-out ; 40 ; ; Average fan-out ; 0.50 ; +---------------------------------------------+--------+ @@ -233,7 +240,7 @@ on the Quartus Prime software download page. +----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ ; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; +----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ -; |assignment2 ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; |assignment2 ; assignment2 ; work ; +; |assignment2 ; 0 (0) ; 0 (0) ; 0 ; 0 ; 40 ; 0 ; |assignment2 ; assignment2 ; work ; +----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -347,6 +354,58 @@ Note: In order to hide this table in the UI and the text report file, please set Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". ++-----------------------------------------------------------------------+ +; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit3" ; ++---------+-------+----------+------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+-------+----------+------------------------------------------+ +; rbi_inv ; Input ; Info ; Stuck at GND ; ++---------+-------+----------+------------------------------------------+ + + ++-----------------------------------------------------------------------+ +; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit2" ; ++---------+-------+----------+------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+-------+----------+------------------------------------------+ +; rbi_inv ; Input ; Info ; Stuck at GND ; ++---------+-------+----------+------------------------------------------+ + + ++-----------------------------------------------------------------------+ +; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit1" ; ++---------+-------+----------+------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+-------+----------+------------------------------------------+ +; rbi_inv ; Input ; Info ; Stuck at GND ; ++---------+-------+----------+------------------------------------------+ + + ++-----------------------------------------------------------------------+ +; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit0" ; ++---------+-------+----------+------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+-------+----------+------------------------------------------+ +; rbi_inv ; Input ; Info ; Stuck at GND ; ++---------+-------+----------+------------------------------------------+ + + ++------------------------------------------------------+ +; Port Connectivity Checks: "seven_seg_4digit:display" ; ++-------------+-------+----------+---------------------+ +; Port ; Type ; Severity ; Details ; ++-------------+-------+----------+---------------------+ +; num[15..14] ; Input ; Info ; Stuck at VCC ; +; num[9..8] ; Input ; Info ; Stuck at VCC ; +; num[13..10] ; Input ; Info ; Stuck at GND ; +; num[5..2] ; Input ; Info ; Stuck at GND ; +; num[7] ; Input ; Info ; Stuck at GND ; +; num[6] ; Input ; Info ; Stuck at VCC ; +; num[1] ; Input ; Info ; Stuck at VCC ; +; num[0] ; Input ; Info ; Stuck at GND ; ++-------------+-------+----------+---------------------+ + + +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "shifter:SHIFTER" ; +-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+ @@ -415,14 +474,17 @@ Note: In order to hide this table in the UI and the text report file, please set +-----------------------------------------------------+ ; Post-Synthesis Netlist Statistics for Top Partition ; -+-------------------+---------------------------------+ -; Type ; Count ; -+-------------------+---------------------------------+ -; boundary_port ; 1 ; -; ; ; -; Max LUT depth ; 0.00 ; -; Average LUT depth ; 0.00 ; -+-------------------+---------------------------------+ ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; arriav_lcell_comb ; 2 ; +; normal ; 2 ; +; 0 data inputs ; 2 ; +; boundary_port ; 40 ; +; ; ; +; Max LUT depth ; 0.00 ; +; Average LUT depth ; 0.00 ; ++-----------------------+-----------------------------+ +-------------------------------+ @@ -440,11 +502,11 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Oct 13 15:08:17 2026 + Info: Processing started: Tue Oct 13 16:18:11 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected -Info (12021): Found 11 design units, including 11 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv +Info (12021): Found 13 design units, including 13 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Info (12023): Found entity 1: rom File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 4 Info (12023): Found entity 2: ram File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 4 Info (12023): Found entity 3: register_file File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv Line: 4 @@ -455,200 +517,244 @@ Info (12021): Found 11 design units, including 11 entities, in source file /home Info (12023): Found entity 8: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 3 Info (12023): Found entity 9: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 9 Info (12023): Found entity 10: shifter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv Line: 3 - Info (12023): Found entity 11: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 15 + Info (12023): Found entity 11: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv Line: 3 + Info (12023): Found entity 12: seven_seg_4digit File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv Line: 5 + Info (12023): Found entity 13: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 15 Info (12127): Elaborating entity "assignment2" for the top level hierarchy -Warning (10036): Verilog HDL or VHDL warning at assignment2.sv(37): object "rd" assigned a value but never read File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 37 -Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 40 -Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 41 +Warning (10036): Verilog HDL or VHDL warning at assignment2.sv(54): object "rd" assigned a value but never read File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 54 +Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 57 +Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 59 Warning (10850): Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range [0:1023] File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 16 Warning (10030): Net "mem.data_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9 Warning (10030): Net "mem.waddr_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9 Warning (10030): Net "mem.we_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9 -Info (12128): Elaborating entity "instruction_classifier" for hierarchy "instruction_classifier:INSTRUCTION_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 42 -Info (12128): Elaborating entity "instruction_module_classifier" for hierarchy "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 43 -Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 49 -Info (12128): Elaborating entity "alu" for hierarchy "alu:ALU" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 +Info (12128): Elaborating entity "instruction_classifier" for hierarchy "instruction_classifier:INSTRUCTION_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 61 +Info (12128): Elaborating entity "instruction_module_classifier" for hierarchy "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 68 +Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 74 +Info (12128): Elaborating entity "alu" for hierarchy "alu:ALU" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 77 Info (12128): Elaborating entity "asu" for hierarchy "alu:ALU|asu:adder_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 18 Info (12128): Elaborating entity "lu" for hierarchy "alu:ALU|lu:logic_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 21 -Info (12128): Elaborating entity "shifter" for hierarchy "shifter:SHIFTER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 55 +Info (12128): Elaborating entity "shifter" for hierarchy "shifter:SHIFTER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 80 +Info (12128): Elaborating entity "seven_seg_4digit" for hierarchy "seven_seg_4digit:display" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 93 +Info (12128): Elaborating entity "seven_seg" for hierarchy "seven_seg_4digit:display|seven_seg:digit0" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv Line: 18 Warning (12011): Net is missing source, defaulting to GND - Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 + Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 Warning (12011): Net is missing source, defaulting to GND - Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 + Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 Warning (12011): Net is missing source, defaulting to GND - Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 + Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 Warning (12011): Net is missing source, defaulting to GND - Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 + Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 Warning (12011): Net is missing source, defaulting to GND - Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 - Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35 + Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 + Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "out_seg_0[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21 + Warning (13410): Pin "out_seg_0[1]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21 + Warning (13410): Pin "out_seg_0[2]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21 + Warning (13410): Pin "out_seg_0[3]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21 + Warning (13410): Pin "out_seg_0[4]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21 + Warning (13410): Pin "out_seg_0[5]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21 + Warning (13410): Pin "out_seg_0[6]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21 + Warning (13410): Pin "out_seg_0[7]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21 + Warning (13410): Pin "out_seg_1[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22 + Warning (13410): Pin "out_seg_1[1]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22 + Warning (13410): Pin "out_seg_1[2]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22 + Warning (13410): Pin "out_seg_1[3]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22 + Warning (13410): Pin "out_seg_1[4]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22 + Warning (13410): Pin "out_seg_1[5]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22 + Warning (13410): Pin "out_seg_1[6]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22 + Warning (13410): Pin "out_seg_1[7]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22 + Warning (13410): Pin "out_seg_2[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_2[1]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_2[2]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_2[3]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_2[4]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_2[5]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_2[6]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_2[7]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23 + Warning (13410): Pin "out_seg_3[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Warning (13410): Pin "out_seg_3[1]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Warning (13410): Pin "out_seg_3[2]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Warning (13410): Pin "out_seg_3[3]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Warning (13410): Pin "out_seg_3[4]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Warning (13410): Pin "out_seg_3[5]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Warning (13410): Pin "out_seg_3[6]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 + Warning (13410): Pin "out_seg_3[7]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25 Info (17049): 32 registers lost all their fanouts during netlist optimizations. Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL -Warning (21074): Design contains 1 input pin(s) that do not drive logic - Warning (15610): No output dependent on input pin "clk[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 15 -Info (21057): Implemented 1 device resources after synthesis - the final resource count might be different - Info (21058): Implemented 1 input pins - Info (21059): Implemented 0 output pins -Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 174 warnings - Info: Peak virtual memory: 425 megabytes - Info: Processing ended: Tue Oct 13 15:08:28 2026 +Warning (21074): Design contains 8 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "clk[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 16 + Warning (15610): No output dependent on input pin "HID_Register[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 17 + Warning (15610): No output dependent on input pin "HID_Register[1]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 17 + Warning (15610): No output dependent on input pin "HID_Register[2]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 17 + Warning (15610): No output dependent on input pin "HID_Register[3]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 17 + Warning (15610): No output dependent on input pin "HID_Register[4]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 17 + Warning (15610): No output dependent on input pin "HID_PC[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 18 + Warning (15610): No output dependent on input pin "HID_Hi_Low[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 19 +Info (21057): Implemented 40 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 8 input pins + Info (21059): Implemented 32 output pins +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 214 warnings + Info: Peak virtual memory: 423 megabytes + Info: Processing ended: Tue Oct 13 16:18:22 2026 Info: Elapsed time: 00:00:11 - Info: Total CPU time (on all processors): 00:00:24 + Info: Total CPU time (on all processors): 00:00:25 diff --git a/Quartus/A2/output_files/assignment2.map.summary b/Quartus/A2/output_files/assignment2.map.summary index fb19294..0bfa021 100644 --- a/Quartus/A2/output_files/assignment2.map.summary +++ b/Quartus/A2/output_files/assignment2.map.summary @@ -1,11 +1,11 @@ -Analysis & Synthesis Status : Successful - Tue Oct 13 15:08:28 2026 +Analysis & Synthesis Status : Successful - Tue Oct 13 16:18:22 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : assignment2 Top-level Entity Name : assignment2 Family : Cyclone V Logic utilization (in ALMs) : N/A Total registers : 0 -Total pins : 1 +Total pins : 40 Total virtual pins : 0 Total block memory bits : 0 Total DSP Blocks : 0 diff --git a/Quartus/A2/output_files/assignment2.pin b/Quartus/A2/output_files/assignment2.pin index 55e64f0..882ecda 100644 --- a/Quartus/A2/output_files/assignment2.pin +++ b/Quartus/A2/output_files/assignment2.pin @@ -29,8 +29,8 @@ -- VCCIO : Dedicated power pin, which MUST be connected to VCC -- of its bank. -- Bank 3A: 2.5V - -- Bank 3B: 2.5V - -- Bank 4A: 2.5V + -- Bank 3B: 1.2V + -- Bank 4A: 1.2V -- Bank 5A: 2.5V -- Bank 5B: 2.5V -- Bank 6A: 2.5V @@ -109,7 +109,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3A : VCC_AUX : AA8 : power : : 2.5V : : VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : : -VCCIO3B : AA10 : power : : 2.5V : 3B : +VCCIO3B : AA10 : power : : 1.2V : 3B : VCCPD3B4A : AA11 : power : : 2.5V : 3B, 4A : NC : AA12 : : : : : VCCPD3B4A : AA13 : power : : 2.5V : 3B, 4A : @@ -117,12 +117,12 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : GND : AA15 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A : VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A : +out_seg_1[1] : AA18 : output : 1.2 V : : 4A : Y VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A : -VCCIO4A : AA20 : power : : 2.5V : 4A : +VCCIO4A : AA20 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A : +out_seg_3[4] : AA22 : output : 2.5 V : : 5A : Y +out_seg_3[3] : AA23 : output : 2.5 V : : 5A : Y RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5B : GND : AA25 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B : @@ -135,16 +135,16 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : NC : AB7 : : : : : GND : AB8 : gnd : : : : VCCPD3A : AB9 : power : : 2.5V : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3B : +HID_Register[0] : AB10 : input : 1.2 V : : 3B : Y RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B : -VCCIO4A : AB13 : power : : 2.5V : 4A : +VCCIO4A : AB13 : power : : 1.2V : 4A : VCC_AUX : AB14 : power : : 2.5V : : RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A : GND : AB18 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4A : +out_seg_1[3] : AB19 : output : 1.2 V : : 4A : Y VCC_AUX : AB20 : power : : 2.5V : : VCCPD3B4A : AB21 : power : : 2.5V : 3B, 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4A : @@ -159,23 +159,23 @@ GXB_NC : AC4 : : : GND : AC5 : gnd : : : : VCCIO3A : AC6 : power : : 2.5V : 3A : VREFB3AN0 : AC7 : power : : : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3B : +HID_Hi_Low[0] : AC8 : input : 1.2 V : : 3B : Y RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3B : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3B : +HID_Register[2] : AC10 : input : 1.2 V : : 3B : Y GND : AC11 : gnd : : : : VREFB3BN0 : AC12 : power : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AC13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4A : -VCCIO4A : AC16 : power : : 2.5V : 4A : +VCCIO4A : AC16 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4A : +out_seg_1[6] : AC19 : output : 1.2 V : : 4A : Y RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A : GND : AC21 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 5A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 5A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5A : +out_seg_3[7] : AC22 : output : 2.5 V : : 5A : Y +out_seg_3[6] : AC23 : output : 2.5 V : : 5A : Y +out_seg_3[5] : AC24 : output : 2.5 V : : 5A : Y RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5B : GND : AC26 : gnd : : : : GND : AD1 : : : : B0L : @@ -183,10 +183,10 @@ GND : AD2 : : : GND : AD3 : gnd : : : : GND : AD4 : gnd : : : : AS_DATA1, DATA1 : AD5 : : : : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A : +out_seg_2[2] : AD6 : output : 2.5 V : : 3A : Y +out_seg_2[1] : AD7 : output : 2.5 V : : 3A : Y RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B : -VCCIO3B : AD9 : power : : 2.5V : 3B : +VCCIO3B : AD9 : power : : 1.2V : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 4A : @@ -196,14 +196,14 @@ VREFB4AN0 : AD15 : power : : RESERVED_INPUT_WITH_WEAK_PULLUP : AD16 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4A : -VCCIO4A : AD19 : power : : 2.5V : 4A : +VCCIO4A : AD19 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD23 : : : : 4A : GND : AD24 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5B : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 4A : +out_seg_1[2] : AD26 : output : 1.2 V : : 4A : Y GND : AE1 : gnd : : : : GND : AE2 : gnd : : : : GXB_NC : AE3 : : : : B0L : @@ -215,21 +215,21 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 4A : -VCCIO4A : AE12 : power : : 2.5V : 4A : +VCCIO4A : AE12 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A : GND : AE17 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A : +HID_Register[4] : AE19 : input : 1.2 V : : 4A : Y RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4A : -VCCIO4A : AE22 : power : : 2.5V : 4A : +VCCIO4A : AE22 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 4A : +out_seg_1[5] : AE25 : output : 1.2 V : : 4A : Y +out_seg_1[4] : AE26 : output : 1.2 V : : 4A : Y GND : AF2 : gnd : : : : GND : AF3 : gnd : : : : GND : AF4 : gnd : : : : @@ -243,7 +243,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A : -VCCIO4A : AF15 : power : : 2.5V : 4A : +VCCIO4A : AF15 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A : @@ -252,7 +252,7 @@ GND : AF20 : gnd : : RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A : +out_seg_1[7] : AF24 : output : 1.2 V : : 4A : Y GND : AF25 : gnd : : : : RREF : B1 : : : : : GND : B2 : gnd : : : : @@ -312,7 +312,7 @@ GND : D3 : gnd : : GND : D4 : gnd : : : : nCE : D5 : : : : 9A : RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A : -RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A : +out_seg_1[0] : D7 : output : 2.5 V : : 8A : N RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8A : VCCIO8A : D9 : power : : 2.5V : 8A : RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 7A : @@ -423,11 +423,11 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : VCCIO7A : H11 : power : : 2.5V : 7A : RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7A : RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7A : -RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7A : +out_seg_3[0] : H14 : output : 2.5 V : : 7A : N RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7A : GND : H16 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7A : -RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7A : +out_seg_2[0] : H18 : output : 2.5 V : : 7A : N RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6A : RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6A : VCCIO6A : H21 : power : : 2.5V : 6A : @@ -460,7 +460,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : VCCPD6A : J22 : power : : 2.5V : 6A : RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A : VCCIO6A : J24 : power : : 2.5V : 6A : -RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A : +out_seg_0[0] : J25 : output : 2.5 V : : 6A : N RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A : GXB_NC : K1 : : : : B1L : GXB_NC : K2 : : : : B1L : @@ -534,7 +534,7 @@ GND : M17 : gnd : : VCC : M18 : power : : 1.1V : : GND : M19 : gnd : : : : VCC : M20 : power : : 1.1V : : -clk[0] : M21 : input : 2.5 V : : 6A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6A : RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A : VCCIO6A : M23 : power : : 2.5V : 6A : RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6A : @@ -651,7 +651,7 @@ GND : U4 : gnd : : VCCE_GXBL : U5 : power : : 1.1V : : AS_DATA3, DATA3 : U6 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A : -VCCIO3B : U8 : power : : 2.5V : 3B : +VCCIO3B : U8 : power : : 1.2V : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B : @@ -661,9 +661,9 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4A : -VCCIO4A : U18 : power : : 2.5V : 4A : +VCCIO4A : U18 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A : -RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A : +out_seg_2[3] : U20 : output : 2.5 V : : 5A : Y VCCPD5A : U21 : power : : 2.5V : 5A : RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5A : GND : U23 : gnd : : : : @@ -679,19 +679,19 @@ GND : V6 : : : TDO : V7 : output : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3B : -RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3B : -VCCIO3B : V11 : power : : 2.5V : 3B : +HID_Register[1] : V10 : input : 1.2 V : : 3B : Y +VCCIO3B : V11 : power : : 1.2V : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4A : GND : V16 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : V19 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5A : +out_seg_0[3] : V17 : output : 1.2 V : : 4A : Y +out_seg_0[2] : V18 : output : 1.2 V : : 4A : Y +out_seg_0[1] : V19 : output : 1.2 V : : 4A : Y +out_seg_2[5] : V20 : output : 2.5 V : : 5A : Y VCCIO5A : V21 : power : : 2.5V : 5A : -RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5A : +out_seg_2[4] : V22 : output : 2.5 V : : 5A : Y RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5B : RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5B : RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B : @@ -706,17 +706,17 @@ VCCA_FPLL : W7 : power : : 2.5V RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A : GND : W9 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3B : -RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B : +HID_PC[0] : W11 : input : 1.2 V : : 3B : Y RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A : -VCCIO4A : W14 : power : : 2.5V : 4A : +VCCIO4A : W14 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4A : +out_seg_0[4] : W18 : output : 1.2 V : : 4A : Y GND : W19 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A : -RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A : +out_seg_2[7] : W20 : output : 2.5 V : : 5A : Y +out_seg_2[6] : W21 : output : 2.5 V : : 5A : Y VCCPGM : W22 : power : : 1.8V/2.5V/3.0V/3.3V : : VREFB5AN0 : W23 : power : : : 5A : VCCIO5B : W24 : power : : 2.5V : 5B : @@ -732,19 +732,19 @@ VCCIO3A : Y7 : power : : 2.5V RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y9 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3B : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3B : +HID_Register[3] : Y11 : input : 1.2 V : : 3B : Y GND : Y12 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A : -VCCIO4A : Y17 : power : : 2.5V : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 4A : +clk[0] : Y16 : input : 1.2 V : : 4A : Y +VCCIO4A : Y17 : power : : 1.2V : 4A : +out_seg_0[7] : Y18 : output : 1.2 V : : 4A : Y +out_seg_0[6] : Y19 : output : 1.2 V : : 4A : Y +out_seg_0[5] : Y20 : output : 1.2 V : : 4A : Y VCCA_FPLL : Y21 : power : : 2.5V : : GND : Y22 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A : +out_seg_3[2] : Y23 : output : 2.5 V : : 5A : Y +out_seg_3[1] : Y24 : output : 2.5 V : : 5A : Y RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5B : RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B : diff --git a/Quartus/A2/output_files/assignment2.sof b/Quartus/A2/output_files/assignment2.sof index b532014..2e245b4 100644 Binary files a/Quartus/A2/output_files/assignment2.sof and b/Quartus/A2/output_files/assignment2.sof differ diff --git a/Quartus/A2/output_files/assignment2.sta.rpt b/Quartus/A2/output_files/assignment2.sta.rpt index fb3c0d2..10b7abf 100644 --- a/Quartus/A2/output_files/assignment2.sta.rpt +++ b/Quartus/A2/output_files/assignment2.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for assignment2 -Tue Oct 13 15:09:06 2026 +Tue Oct 13 16:19:07 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -99,7 +99,7 @@ on the Quartus Prime software download page. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.1% ; +; Processor 2 ; 0.0% ; +----------------------------+-------------+ @@ -281,48 +281,220 @@ No synchronizer chains to report. +------------------+-------+------+----------+---------+---------------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Board Trace Model Assignments ; -+-----+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ -; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; -+-----+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; out_seg_0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_0[1] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_0[2] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_0[3] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_0[4] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_0[5] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_0[6] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_0[7] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[1] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[2] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[3] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[4] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[5] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[6] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[7] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_2[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_2[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_2[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_2[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_2[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_2[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_2[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_2[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_3[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_3[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_3[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_3[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_3[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_3[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_3[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_3[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ -+-----------------------------------------------------------+ -; Input Transition Times ; -+--------+--------------+-----------------+-----------------+ -; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; -+--------+--------------+-----------------+-----------------+ -; clk[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -+--------+--------------+-----------------+-----------------+ ++--------------------------------------------------------------------+ +; Input Transition Times ; ++-----------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-----------------+--------------+-----------------+-----------------+ +; clk[0] ; 1.2 V ; 960 ps ; 960 ps ; +; HID_Register[0] ; 1.2 V ; 960 ps ; 960 ps ; +; HID_Register[1] ; 1.2 V ; 960 ps ; 960 ps ; +; HID_Register[2] ; 1.2 V ; 960 ps ; 960 ps ; +; HID_Register[3] ; 1.2 V ; 960 ps ; 960 ps ; +; HID_Register[4] ; 1.2 V ; 960 ps ; 960 ps ; +; HID_PC[0] ; 1.2 V ; 960 ps ; 960 ps ; +; HID_Hi_Low[0] ; 1.2 V ; 960 ps ; 960 ps ; ++-----------------+--------------+-----------------+-----------------+ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Slow 1100mv 0c Model) ; -+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; out_seg_0[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; +; out_seg_0[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; +; out_seg_0[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; +; out_seg_0[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; +; out_seg_0[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; +; out_seg_0[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; +; out_seg_0[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; +; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; +; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; +; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; +; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; +; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; +; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; +; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; +; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; +; out_seg_2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; out_seg_2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; out_seg_2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; +; out_seg_2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; +; out_seg_2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; +; out_seg_2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; +; out_seg_2[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; +; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; +; out_seg_3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; out_seg_3[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; out_seg_3[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; out_seg_3[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; out_seg_3[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; out_seg_3[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; out_seg_3[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Slow 1100mv 85c Model) ; -+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; out_seg_0[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; +; out_seg_0[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; +; out_seg_0[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; +; out_seg_0[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; +; out_seg_0[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; +; out_seg_0[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; +; out_seg_0[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; +; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; +; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ; +; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ; +; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ; +; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ; +; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ; +; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ; +; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; +; out_seg_2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; out_seg_2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; out_seg_2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; +; out_seg_2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; +; out_seg_2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; +; out_seg_2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; +; out_seg_2[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; +; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; +; out_seg_3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; out_seg_3[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; out_seg_3[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; out_seg_3[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; out_seg_3[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; out_seg_3[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; out_seg_3[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Fast 1100mv 0c Model) ; -+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; out_seg_0[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; +; out_seg_0[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; +; out_seg_0[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; +; out_seg_0[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; +; out_seg_0[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; +; out_seg_0[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; +; out_seg_0[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; +; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; +; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; +; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; +; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; +; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; +; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; +; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; +; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; out_seg_2[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; out_seg_2[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; out_seg_2[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; out_seg_2[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; out_seg_2[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; out_seg_2[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; out_seg_2[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; out_seg_3[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; out_seg_3[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; out_seg_3[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; out_seg_3[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; out_seg_3[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; out_seg_3[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; out_seg_3[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Fast 1100mv 85c Model) ; -+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; out_seg_0[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; +; out_seg_0[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; +; out_seg_0[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; +; out_seg_0[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; +; out_seg_0[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; +; out_seg_0[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; +; out_seg_0[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; +; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; +; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; +; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; +; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; +; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; +; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; +; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; +; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; out_seg_2[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; out_seg_2[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; out_seg_2[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; out_seg_2[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; out_seg_2[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; out_seg_2[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; out_seg_2[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; out_seg_3[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; out_seg_3[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; out_seg_3[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; out_seg_3[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; out_seg_3[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; out_seg_3[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; out_seg_3[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ------------------- @@ -363,7 +535,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Oct 13 15:09:02 2026 + Info: Processing started: Tue Oct 13 16:19:02 2026 Info: Command: quartus_sta assignment2 -c assignment2 Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -423,9 +595,9 @@ Info (332140): No Minimum Pulse Width paths to report Info (332101): Design is fully constrained for setup requirements Info (332101): Design is fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 718 megabytes - Info: Processing ended: Tue Oct 13 15:09:06 2026 - Info: Elapsed time: 00:00:04 - Info: Total CPU time (on all processors): 00:00:04 + Info: Peak virtual memory: 757 megabytes + Info: Processing ended: Tue Oct 13 16:19:07 2026 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:06 diff --git a/Quartus/A2/simulation/questa/assignment2.svo b/Quartus/A2/simulation/questa/assignment2.svo index d81e8de..14687a1 100644 --- a/Quartus/A2/simulation/questa/assignment2.svo +++ b/Quartus/A2/simulation/questa/assignment2.svo @@ -17,7 +17,7 @@ // PROGRAM "Quartus Prime" // VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" -// DATE "10/13/2026 15:09:08" +// DATE "10/13/2026 16:19:10" // // Device: Altera 5CGXFC5C6F27C7 Package FBGA672 @@ -30,11 +30,64 @@ `timescale 1 ps/ 1 ps module assignment2 ( - clk); -input logic [0:0] clk ; + clk, + HID_Register, + HID_PC, + HID_Hi_Low, + out_seg_0, + out_seg_1, + out_seg_2, + out_seg_3); +input [0:0] clk; +input [4:0] HID_Register; +input [0:0] HID_PC; +input [0:0] HID_Hi_Low; +output [7:0] out_seg_0; +output [7:0] out_seg_1; +output [7:0] out_seg_2; +output [7:0] out_seg_3; // Design Ports Information -// clk[0] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default +// clk[0] => Location: PIN_Y16, I/O Standard: 1.2 V, Current Strength: Default +// HID_Register[0] => Location: PIN_AB10, I/O Standard: 1.2 V, Current Strength: Default +// HID_Register[1] => Location: PIN_V10, I/O Standard: 1.2 V, Current Strength: Default +// HID_Register[2] => Location: PIN_AC10, I/O Standard: 1.2 V, Current Strength: Default +// HID_Register[3] => Location: PIN_Y11, I/O Standard: 1.2 V, Current Strength: Default +// HID_Register[4] => Location: PIN_AE19, I/O Standard: 1.2 V, Current Strength: Default +// HID_PC[0] => Location: PIN_W11, I/O Standard: 1.2 V, Current Strength: Default +// HID_Hi_Low[0] => Location: PIN_AC8, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_0[0] => Location: PIN_J25, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_0[1] => Location: PIN_V19, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_0[2] => Location: PIN_V18, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_0[3] => Location: PIN_V17, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_0[4] => Location: PIN_W18, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_0[5] => Location: PIN_Y20, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_0[6] => Location: PIN_Y19, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_0[7] => Location: PIN_Y18, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_1[0] => Location: PIN_D7, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_1[1] => Location: PIN_AA18, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_1[2] => Location: PIN_AD26, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_1[3] => Location: PIN_AB19, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_1[4] => Location: PIN_AE26, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_1[5] => Location: PIN_AE25, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_1[6] => Location: PIN_AC19, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_1[7] => Location: PIN_AF24, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_2[0] => Location: PIN_H18, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_2[1] => Location: PIN_AD7, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_2[2] => Location: PIN_AD6, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_2[3] => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_2[4] => Location: PIN_V22, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_2[5] => Location: PIN_V20, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_2[6] => Location: PIN_W21, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_2[7] => Location: PIN_W20, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_3[0] => Location: PIN_H14, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_3[1] => Location: PIN_Y24, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_3[2] => Location: PIN_Y23, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_3[3] => Location: PIN_AA23, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_3[4] => Location: PIN_AA22, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_3[5] => Location: PIN_AC24, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_3[6] => Location: PIN_AC23, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_3[7] => Location: PIN_AC22, I/O Standard: 2.5 V, Current Strength: Default wire gnd; @@ -49,10 +102,529 @@ tri1 devclrn; tri1 devpor; tri1 devoe; wire \clk[0]~input_o ; +wire \HID_Register[0]~input_o ; +wire \HID_Register[1]~input_o ; +wire \HID_Register[2]~input_o ; +wire \HID_Register[3]~input_o ; +wire \HID_Register[4]~input_o ; +wire \HID_PC[0]~input_o ; +wire \HID_Hi_Low[0]~input_o ; wire \~QUARTUS_CREATED_GND~I_combout ; -// Location: IOIBUF_X68_Y32_N61 +// Location: IOOBUF_X68_Y32_N79 +cyclonev_io_obuf \out_seg_0[0]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_0[0]), + .obar()); +// synopsys translate_off +defparam \out_seg_0[0]~output .bus_hold = "false"; +defparam \out_seg_0[0]~output .open_drain_output = "false"; +defparam \out_seg_0[0]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X66_Y0_N2 +cyclonev_io_obuf \out_seg_0[1]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_0[1]), + .obar()); +// synopsys translate_off +defparam \out_seg_0[1]~output .bus_hold = "false"; +defparam \out_seg_0[1]~output .open_drain_output = "false"; +defparam \out_seg_0[1]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X64_Y0_N2 +cyclonev_io_obuf \out_seg_0[2]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_0[2]), + .obar()); +// synopsys translate_off +defparam \out_seg_0[2]~output .bus_hold = "false"; +defparam \out_seg_0[2]~output .open_drain_output = "false"; +defparam \out_seg_0[2]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X64_Y0_N19 +cyclonev_io_obuf \out_seg_0[3]~output ( + .i(vcc), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_0[3]), + .obar()); +// synopsys translate_off +defparam \out_seg_0[3]~output .bus_hold = "false"; +defparam \out_seg_0[3]~output .open_drain_output = "false"; +defparam \out_seg_0[3]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X66_Y0_N19 +cyclonev_io_obuf \out_seg_0[4]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_0[4]), + .obar()); +// synopsys translate_off +defparam \out_seg_0[4]~output .bus_hold = "false"; +defparam \out_seg_0[4]~output .open_drain_output = "false"; +defparam \out_seg_0[4]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X65_Y0_N2 +cyclonev_io_obuf \out_seg_0[5]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_0[5]), + .obar()); +// synopsys translate_off +defparam \out_seg_0[5]~output .bus_hold = "false"; +defparam \out_seg_0[5]~output .open_drain_output = "false"; +defparam \out_seg_0[5]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X65_Y0_N19 +cyclonev_io_obuf \out_seg_0[6]~output ( + .i(vcc), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_0[6]), + .obar()); +// synopsys translate_off +defparam \out_seg_0[6]~output .bus_hold = "false"; +defparam \out_seg_0[6]~output .open_drain_output = "false"; +defparam \out_seg_0[6]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X62_Y0_N42 +cyclonev_io_obuf \out_seg_0[7]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_0[7]), + .obar()); +// synopsys translate_off +defparam \out_seg_0[7]~output .bus_hold = "false"; +defparam \out_seg_0[7]~output .open_drain_output = "false"; +defparam \out_seg_0[7]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X17_Y61_N76 +cyclonev_io_obuf \out_seg_1[0]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[0]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[0]~output .bus_hold = "false"; +defparam \out_seg_1[0]~output .open_drain_output = "false"; +defparam \out_seg_1[0]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X62_Y0_N59 +cyclonev_io_obuf \out_seg_1[1]~output ( + .i(vcc), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[1]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[1]~output .bus_hold = "false"; +defparam \out_seg_1[1]~output .open_drain_output = "false"; +defparam \out_seg_1[1]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X64_Y0_N36 +cyclonev_io_obuf \out_seg_1[2]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[2]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[2]~output .bus_hold = "false"; +defparam \out_seg_1[2]~output .open_drain_output = "false"; +defparam \out_seg_1[2]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X65_Y0_N36 +cyclonev_io_obuf \out_seg_1[3]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[3]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[3]~output .bus_hold = "false"; +defparam \out_seg_1[3]~output .open_drain_output = "false"; +defparam \out_seg_1[3]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X64_Y0_N53 +cyclonev_io_obuf \out_seg_1[4]~output ( + .i(vcc), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[4]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[4]~output .bus_hold = "false"; +defparam \out_seg_1[4]~output .open_drain_output = "false"; +defparam \out_seg_1[4]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X62_Y0_N76 +cyclonev_io_obuf \out_seg_1[5]~output ( + .i(vcc), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[5]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[5]~output .bus_hold = "false"; +defparam \out_seg_1[5]~output .open_drain_output = "false"; +defparam \out_seg_1[5]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X65_Y0_N53 +cyclonev_io_obuf \out_seg_1[6]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[6]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[6]~output .bus_hold = "false"; +defparam \out_seg_1[6]~output .open_drain_output = "false"; +defparam \out_seg_1[6]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X62_Y0_N93 +cyclonev_io_obuf \out_seg_1[7]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[7]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[7]~output .bus_hold = "false"; +defparam \out_seg_1[7]~output .open_drain_output = "false"; +defparam \out_seg_1[7]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X64_Y61_N2 +cyclonev_io_obuf \out_seg_2[0]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_2[0]), + .obar()); +// synopsys translate_off +defparam \out_seg_2[0]~output .bus_hold = "false"; +defparam \out_seg_2[0]~output .open_drain_output = "false"; +defparam \out_seg_2[0]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y0_N36 +cyclonev_io_obuf \out_seg_2[1]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_2[1]), + .obar()); +// synopsys translate_off +defparam \out_seg_2[1]~output .bus_hold = "false"; +defparam \out_seg_2[1]~output .open_drain_output = "false"; +defparam \out_seg_2[1]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y0_N53 +cyclonev_io_obuf \out_seg_2[2]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_2[2]), + .obar()); +// synopsys translate_off +defparam \out_seg_2[2]~output .bus_hold = "false"; +defparam \out_seg_2[2]~output .open_drain_output = "false"; +defparam \out_seg_2[2]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y13_N22 +cyclonev_io_obuf \out_seg_2[3]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_2[3]), + .obar()); +// synopsys translate_off +defparam \out_seg_2[3]~output .bus_hold = "false"; +defparam \out_seg_2[3]~output .open_drain_output = "false"; +defparam \out_seg_2[3]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y12_N5 +cyclonev_io_obuf \out_seg_2[4]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_2[4]), + .obar()); +// synopsys translate_off +defparam \out_seg_2[4]~output .bus_hold = "false"; +defparam \out_seg_2[4]~output .open_drain_output = "false"; +defparam \out_seg_2[4]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y10_N62 +cyclonev_io_obuf \out_seg_2[5]~output ( + .i(vcc), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_2[5]), + .obar()); +// synopsys translate_off +defparam \out_seg_2[5]~output .bus_hold = "false"; +defparam \out_seg_2[5]~output .open_drain_output = "false"; +defparam \out_seg_2[5]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y11_N22 +cyclonev_io_obuf \out_seg_2[6]~output ( + .i(vcc), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_2[6]), + .obar()); +// synopsys translate_off +defparam \out_seg_2[6]~output .bus_hold = "false"; +defparam \out_seg_2[6]~output .open_drain_output = "false"; +defparam \out_seg_2[6]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y11_N5 +cyclonev_io_obuf \out_seg_2[7]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_2[7]), + .obar()); +// synopsys translate_off +defparam \out_seg_2[7]~output .bus_hold = "false"; +defparam \out_seg_2[7]~output .open_drain_output = "false"; +defparam \out_seg_2[7]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X53_Y61_N2 +cyclonev_io_obuf \out_seg_3[0]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_3[0]), + .obar()); +// synopsys translate_off +defparam \out_seg_3[0]~output .bus_hold = "false"; +defparam \out_seg_3[0]~output .open_drain_output = "false"; +defparam \out_seg_3[0]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y13_N56 +cyclonev_io_obuf \out_seg_3[1]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_3[1]), + .obar()); +// synopsys translate_off +defparam \out_seg_3[1]~output .bus_hold = "false"; +defparam \out_seg_3[1]~output .open_drain_output = "false"; +defparam \out_seg_3[1]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y13_N39 +cyclonev_io_obuf \out_seg_3[2]~output ( + .i(vcc), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_3[2]), + .obar()); +// synopsys translate_off +defparam \out_seg_3[2]~output .bus_hold = "false"; +defparam \out_seg_3[2]~output .open_drain_output = "false"; +defparam \out_seg_3[2]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y11_N56 +cyclonev_io_obuf \out_seg_3[3]~output ( + .i(vcc), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_3[3]), + .obar()); +// synopsys translate_off +defparam \out_seg_3[3]~output .bus_hold = "false"; +defparam \out_seg_3[3]~output .open_drain_output = "false"; +defparam \out_seg_3[3]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y11_N39 +cyclonev_io_obuf \out_seg_3[4]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_3[4]), + .obar()); +// synopsys translate_off +defparam \out_seg_3[4]~output .bus_hold = "false"; +defparam \out_seg_3[4]~output .open_drain_output = "false"; +defparam \out_seg_3[4]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y12_N39 +cyclonev_io_obuf \out_seg_3[5]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_3[5]), + .obar()); +// synopsys translate_off +defparam \out_seg_3[5]~output .bus_hold = "false"; +defparam \out_seg_3[5]~output .open_drain_output = "false"; +defparam \out_seg_3[5]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y10_N96 +cyclonev_io_obuf \out_seg_3[6]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_3[6]), + .obar()); +// synopsys translate_off +defparam \out_seg_3[6]~output .bus_hold = "false"; +defparam \out_seg_3[6]~output .open_drain_output = "false"; +defparam \out_seg_3[6]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y10_N79 +cyclonev_io_obuf \out_seg_3[7]~output ( + .i(vcc), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_3[7]), + .obar()); +// synopsys translate_off +defparam \out_seg_3[7]~output .bus_hold = "false"; +defparam \out_seg_3[7]~output .open_drain_output = "false"; +defparam \out_seg_3[7]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOIBUF_X46_Y0_N18 cyclonev_io_ibuf \clk[0]~input ( .i(clk[0]), .ibar(gnd), @@ -63,7 +635,84 @@ defparam \clk[0]~input .bus_hold = "false"; defparam \clk[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LABCELL_X9_Y53_N0 +// Location: IOIBUF_X12_Y0_N35 +cyclonev_io_ibuf \HID_Register[0]~input ( + .i(HID_Register[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\HID_Register[0]~input_o )); +// synopsys translate_off +defparam \HID_Register[0]~input .bus_hold = "false"; +defparam \HID_Register[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X17_Y0_N75 +cyclonev_io_ibuf \HID_Register[1]~input ( + .i(HID_Register[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\HID_Register[1]~input_o )); +// synopsys translate_off +defparam \HID_Register[1]~input .bus_hold = "false"; +defparam \HID_Register[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X12_Y0_N52 +cyclonev_io_ibuf \HID_Register[2]~input ( + .i(HID_Register[2]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\HID_Register[2]~input_o )); +// synopsys translate_off +defparam \HID_Register[2]~input .bus_hold = "false"; +defparam \HID_Register[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X10_Y0_N58 +cyclonev_io_ibuf \HID_Register[3]~input ( + .i(HID_Register[3]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\HID_Register[3]~input_o )); +// synopsys translate_off +defparam \HID_Register[3]~input .bus_hold = "false"; +defparam \HID_Register[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X50_Y0_N35 +cyclonev_io_ibuf \HID_Register[4]~input ( + .i(HID_Register[4]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\HID_Register[4]~input_o )); +// synopsys translate_off +defparam \HID_Register[4]~input .bus_hold = "false"; +defparam \HID_Register[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X10_Y0_N41 +cyclonev_io_ibuf \HID_PC[0]~input ( + .i(HID_PC[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\HID_PC[0]~input_o )); +// synopsys translate_off +defparam \HID_PC[0]~input .bus_hold = "false"; +defparam \HID_PC[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y0_N52 +cyclonev_io_ibuf \HID_Hi_Low[0]~input ( + .i(HID_Hi_Low[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\HID_Hi_Low[0]~input_o )); +// synopsys translate_off +defparam \HID_Hi_Low[0]~input .bus_hold = "false"; +defparam \HID_Hi_Low[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X56_Y45_N3 cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I ( // Equation(s): diff --git a/modules/assignment2.sv b/modules/assignment2.sv index d462d96..c70ebf1 100644 --- a/modules/assignment2.sv +++ b/modules/assignment2.sv @@ -9,54 +9,88 @@ `include "instruction_module_classifier.sv" `include "alu.sv" `include "shifter.sv" +`include "seven_seg_4digit.sv" - -module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk); - logic [romsz-1:0] pc_addr; - logic [romsz-1:0] pc_addr_write; - logic [0:0] pc_we; - logic [2**width-1:0] instruction; - - logic[0:0] R; - logic[0:0] B1; - logic[0:0] J; - logic[0:0] B2; - logic[0:0] I; - logic[0:0] F; - logic[0:0] M; - - logic [0:0] en_shifter; - logic [0:0] en_jmp; - logic [0:0] en_mul; - logic [0:0] en_alu; - - logic [1:0] flags; - logic [2**width-1:0] rs; - logic [2**width-1:0] rt; - logic [2**width-1:0] rd; - logic [0:0] rd_we; - - instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr); - rom #(romsz, 2**width) ROM (pc_addr, instruction); - instruction_classifier INSTRUCTION_CLASSIFIER(instruction[31:26], R, B1, J, B2, I, F, M); - instruction_module_classifier INSTRUCTION_MODULE_CLASSIFIER(instruction[5:3], en_shifter, en_jmp, en_mul, en_alu); +module assignment2 #(width=5, ramsz=9, romsz=10) ( + input logic [0:0] clk, + input logic [4:0] HID_Register, + input logic [0:0] HID_PC, + input logic [0:0] HID_Hi_Low, + + output logic[7:0] out_seg_0, + output logic[7:0] out_seg_1, + output logic[7:0] out_seg_2, + output logic[7:0] out_seg_3 + ); + // Intermediate for displaying high / low of PC or Register + logic[15:0] PC_Reg_Display; + + // Program / Instruction Counter Intermediates + logic [romsz-1:0] pc_addr; + logic [romsz-1:0] pc_addr_write; + logic [0:0] pc_we; + logic [2**width-1:0] instruction; + + // Instruction Classifier Intermediates + logic[0:0] R; + logic[0:0] B1; + logic[0:0] J; + logic[0:0] B2; + logic[0:0] I; + logic[0:0] F; + logic[0:0] M; + + // Instruction Module Classifier intermediates + logic [0:0] en_shifter; + logic [0:0] en_jmp; + logic [0:0] en_mul; + logic [0:0] en_alu; + + // Register File intermediates + logic [1:0] flags; + logic [2**width-1:0] rs; + logic [2**width-1:0] rt; + logic [2**width-1:0] rd; + logic [0:0] rd_we; + + instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr); + + rom #(romsz, 2**width) ROM (pc_addr, instruction); + + instruction_classifier INSTRUCTION_CLASSIFIER(instruction[31:26], R, B1, J, B2, I, F, M); + + instruction_module_classifier INSTRUCTION_MODULE_CLASSIFIER(instruction[5:3], + en_shifter, + en_jmp, + en_mul, + en_alu + ); - register_file #(width, 5) REGS (clk, - rd_we, instruction[15:11], - rs, instruction[25:21], - rt, instruction[20:16] - ); + register_file #(width, 5) REGS (clk, + rd_we, instruction[15:11], + rs, instruction[25:21], + rt, instruction[20:16] + ); - logic [2**width-1:0] rd_alu; - alu #(width) ALU (instruction[3:0], rs, rt, rd_alu, flags[1:0]); + logic [2**width-1:0] rd_alu; + alu #(width) ALU (instruction[3:0], rs, rt, rd_alu, flags[1:0]); - logic [2**width-1:0] rd_shifter; - shifter #(width) SHIFTER (instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter); + logic [2**width-1:0] rd_shifter; + shifter #(width) SHIFTER (instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter); - assign rd = en_alu - ? rd_alu - : (en_shifter ? rd_shifter : {2**width{1'b0}}); + assign rd = en_alu ? rd_alu : (en_shifter ? rd_shifter : {2**width{1'b0}}); + + // Temporary Test output + assign PC_Reg_Display = 16'hC342; + + seven_seg_4digit display ( + .num(PC_Reg_Display), + .segments0(out_seg_0), + .segments1(out_seg_1), + .segments2(out_seg_2), + .segments3(out_seg_3) + ); endmodule `endif diff --git a/modules/rom.sv b/modules/rom.sv index a07103d..e18e3c7 100644 --- a/modules/rom.sv +++ b/modules/rom.sv @@ -21,3 +21,4 @@ module rom #(parameter m=7,p=4) ( endmodule // end rom module `endif + diff --git a/modules/seven_seg_4digit.sv b/modules/seven_seg_4digit.sv new file mode 100644 index 0000000..3ccedd4 --- /dev/null +++ b/modules/seven_seg_4digit.sv @@ -0,0 +1,44 @@ +`ifndef SEVEN_SEG_4_H_SV +`define SEVEN_SEG_4_H_SV + +`include "seven_seg.sv" +module seven_seg_4digit ( + input logic [15:0] num, + output logic [7:0] segments0, + output logic [7:0] segments1, + output logic [7:0] segments2, + output logic [7:0] segments3 +); + + // Rightmost digit + seven_seg digit0 ( + .num(num[3:0]), + .rbi_inv(1'b0), + .segments(segments0) + ); + + // Second digit from right + seven_seg digit1 ( + .num(num[7:4]), + .rbi_inv(1'b0), + .segments(segments1) + ); + + // Third digit from right + seven_seg digit2 ( + .num(num[11:8]), + .rbi_inv(1'b0), + .segments(segments2) + ); + + // Leftmost digit + seven_seg digit3 ( + .num(num[15:12]), + .rbi_inv(1'b0), + .segments(segments3) + ); + +endmodule + +`endif +