Updated ModelSim Files

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TroubleElectrical committed 2026-09-16 10:15:08 +10:00
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@@ -1,8 +1,8 @@
`ifndef SHIFTER_H_SV
`define SHIFTER_H_SV
module shifter #(width=8)(input logic [2:0] op,
input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B,
output logic[width-1:0] OUT_1);
module shifter #(width=2)(input logic [2:0] op,
input logic[2**width-1:0] A, input logic[2**width-1:0] B, input logic[width-1:0] C,
output logic[2**width-1:0] OUT_1);
always_comb begin
case (op)