diff --git a/ModelSim/asu_tb.sv b/ModelSim/asu_tb.sv index e0285fb..63069d5 100644 --- a/ModelSim/asu_tb.sv +++ b/ModelSim/asu_tb.sv @@ -1,6 +1,6 @@ `include "asu.sv" -module asu_tb #(width=8)(); +module asu_tb #(width=4)(); logic [0:0] op; logic [width-1:0] A; logic [width-1:0] B; diff --git a/ModelSim/shifter.sv b/ModelSim/shifter.sv index 7b84b49..a4070a9 100644 --- a/ModelSim/shifter.sv +++ b/ModelSim/shifter.sv @@ -1,8 +1,8 @@ `ifndef SHIFTER_H_SV `define SHIFTER_H_SV -module shifter #(width=8)(input logic [2:0] op, - input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B, - output logic[width-1:0] OUT_1); +module shifter #(width=2)(input logic [2:0] op, + input logic[2**width-1:0] A, input logic[2**width-1:0] B, input logic[width-1:0] C, + output logic[2**width-1:0] OUT_1); always_comb begin case (op) diff --git a/ModelSim/shifter_tb.sv b/ModelSim/shifter_tb.sv index 2a43af6..105216c 100644 --- a/ModelSim/shifter_tb.sv +++ b/ModelSim/shifter_tb.sv @@ -1,62 +1,62 @@ `include "shifter.sv" -module shifter_tb #(width=8)(); +module shifter_tb #(width=4)(); logic [2:0] op; - logic [width-1:0] Y; - logic [width-1:0] A_in; - logic [$clog2(width)-1:0] B_in; + logic [2**width-1:0] Y; + logic [2**width-1:0] A_in; + logic [2**width-1:0] B_in; logic [width-1:0] C_in; logic [2:0] ops[6]; - logic [width-1:0] A[6]; - logic [$clog2(width)-1:0] B[6]; + logic [2**width-1:0] A[6]; + logic [2**width-1:0] B[6]; logic [width-1:0] C[6]; - logic [width-1:0] Y_exp[6]; + logic [2**width-1:0] Y_exp[6]; - shifter #(width) dut(op, A_in,C_in,B_in,Y); + shifter #(width) dut(op, A_in,B_in,C_in,Y); integer error_count; initial begin // Test left shift by C ops[0] = 3'b000; - A[0] = {{(width-1){1'b0}}, {1'b1}}; + A[0] = {{(2**width-1){1'b0}}, {1'b1}}; C[0] = {{(width-1){1'b0}}, {1'b1}}; - B[0] = {width{1'b0}}; - Y_exp[0] = {{(width-2){1'b0}}, {2'b10}}; + B[0] = {2**width{1'b0}}; + Y_exp[0] = {{(2**width-2){1'b0}}, {2'b10}}; // Test left shift by B ops[1] = 3'b100; - A[1] = {{(width-1){1'b0}}, {1'b1}}; + A[1] = {{(2**width-1){1'b0}}, {1'b1}}; C[1] = {{(width-1){1'b0}}, {1'b1}}; - B[1] = {{($clog2(width)-2){1'b0}}, 2'b10}; - Y_exp[1] = {{(width-3){1'b0}}, {3'b100}}; + B[1] = {{(2**width-2){1'b0}}, 2'b10}; + Y_exp[1] = {{(2**width-3){1'b0}}, {3'b100}}; // Test Logical right shift by C ops[2] = 3'b001; - A[2] = {{(width-2){1'b0}}, {2'b10}}; + A[2] = {{(2**width-2){1'b0}}, {2'b10}}; C[2] = {{(width-1){1'b0}}, {1'b1}}; - B[2] = {width{1'b0}}; - Y_exp[2] = {{(width-1){1'b0}}, {1'b1}}; + B[2] = {2**width{1'b0}}; + Y_exp[2] = {{(2**width-1){1'b0}}, {1'b1}}; // Test Logical right shift by B ops[3] = 3'b101; - A[3] = {{(width-1){1'b0}}, {2'b10}}; + A[3] = {{(2**width-1){1'b0}}, {2'b10}}; C[3] = {{(width-1){1'b0}}, {1'b1}}; - B[3] = {{($clog2(width)-2){1'b0}}, 2'b10}; - Y_exp[3] = {{(width-1){1'b0}}, {1'b0}}; + B[3] = {{(2**width-2){1'b0}}, 2'b10}; + Y_exp[3] = {{(2**width-1){1'b0}}, {1'b0}}; // Test arithmetic shift right by C ops[4] = 3'b011; - A[4] = {{(width-1){1'b1}}, 1'b0}; // -2 + A[4] = {{(2**width-1){1'b1}}, 1'b0}; // -2 C[4] = {{(width-1){1'b0}}, 1'b1}; // 1 - B[4] = {{(width-2){1'b0}}, 2'b10}; // 2 - Y_exp[4] = {width{1'b1}}; // -1 + B[4] = {{(2**width-2){1'b0}}, 2'b10}; // 2 + Y_exp[4] = {2**width{1'b1}}; // -1 // Test arithmetic shift right by B ops[5] = 3'b111; - A[5] = {{(width-2){1'b1}}, 2'b00}; // -4 + A[5] = {{(2**width-2){1'b1}}, 2'b00}; // -4 C[5] = {{(width-1){1'b0}}, 1'b1}; // 1 - B[5] = {{(width-2){1'b0}}, 2'b10}; // 2 - Y_exp[5] = {width{1'b1}}; // -1 + B[5] = {{(2**width-2){1'b0}}, 2'b10}; // 2 + Y_exp[5] = {2**width{1'b1}}; // -1 error_count = 0; $display("Beginning Shifter tests"); diff --git a/Quartus/A1_Q1/db/seven_seg.db_info b/Quartus/A1_Q1/db/seven_seg.db_info index 504b7bb..77bf752 100644 --- a/Quartus/A1_Q1/db/seven_seg.db_info +++ b/Quartus/A1_Q1/db/seven_seg.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Version_Index = 604268800 -Creation_Time = Tue Sep 15 20:07:32 2026 +Creation_Time = Wed Sep 16 09:35:09 2026 diff --git a/Quartus/A1_Q1/db/seven_seg.tmw_info b/Quartus/A1_Q1/db/seven_seg.tmw_info deleted file mode 100644 index 424f727..0000000 --- a/Quartus/A1_Q1/db/seven_seg.tmw_info +++ /dev/null @@ -1,7 +0,0 @@ -start_full_compilation:s:00:00:59 -start_analysis_synthesis:s:00:00:12-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:31-start_full_compilation -start_assembler:s:00:00:07-start_full_compilation -start_timing_analyzer:s:00:00:07-start_full_compilation -start_eda_netlist_writer:s:00:00:02-start_full_compilation diff --git a/Quartus/A1_Q1/seven_seg.qws b/Quartus/A1_Q1/seven_seg.qws index a08287b..1145b54 100644 Binary files a/Quartus/A1_Q1/seven_seg.qws and b/Quartus/A1_Q1/seven_seg.qws differ diff --git a/Quartus/A1_Q1/seven_seg.sv b/Quartus/A1_Q1/seven_seg.sv index 7f9e8ac..b68d559 100644 --- a/Quartus/A1_Q1/seven_seg.sv +++ b/Quartus/A1_Q1/seven_seg.sv @@ -34,8 +34,6 @@ input logic [3:0] b, // left input logic [3:0] a, // right output logic [7:0] seg_b, // left output logic [7:0] seg_a); // right - - logic rbo_b; // seg_b seven_seg left_digit(