TroubleElectrical/FPGA_Uni
1
0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Updated ModelSim Files

Browse Source
This commit is contained in:
TroubleElectrical committed 2026-09-16 10:15:08 +10:00
1 parent 900b544bc6
commit 00167dabc8
7 files changed
+31 -40
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

ModelSim/asu_tb.sv
+1 -1
View File
@@ -1,6 +1,6 @@
`include "asu.sv"
module asu_tb #(width=8)();
module asu_tb #(width=4)();
logic [0:0] op;
logic [width-1:0] A;
logic [width-1:0] B;