38 lines
1.1 KiB
Systemverilog
38 lines
1.1 KiB
Systemverilog
`#include "alu.sv"
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module alu_tb #(width=2)();
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logic [3:0] op_in;
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logic [2**width-1:0] A_in;
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logic [2**width-1:0] B_in;
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logic [2**width-1:0] Y_out;
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logic [1:0] flags_out;
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logic [3:0] ops[1];
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logic [2**width-1:0] A_cases[$size(ops)];
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logic [2**width-1:0] B_cases[$size(ops)];
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logic [2**width-1:0] Y_exp[$size(ops)];
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logic [1:0] flags_exp[$size(ops)];
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alu #(width)(op_in, A_in, B_in, Y_out, flags_out);
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integer error_count;
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initial begin
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error_count = 0;
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$display("Beginning ALU tests");
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for (integer N = 0; N < $size(ops); ++N) begin
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op = ops[N];
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A_in = A_cases[N];
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B_in = B_cases[N];
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#1;
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if (Y_out != Y_exp[N]) begin
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$display("\t\x1b[38;5;9mALU Instruction 0b%b produced 0b%b_%b but 0b%b_%b was expected\x1b[m", op, flags_out, Y_out, flags_exp[N], Y_exp[N]);
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error_count = error_count + 1;
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end
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end
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if (error_count == 0) $display("\x1b[38;5;10mAll ALU tests passing\x1b[m");
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else $display("\x1b[38;5;9m%0d ALU test(s) failing\x1b[m", error_count);
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end
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endmodule |