18 lines
835 B
Systemverilog
18 lines
835 B
Systemverilog
module asu #(parameter width = 2)(
|
|
input logic [0:0] op,
|
|
input logic[2**width-1:0] A, input logic[2**width-1:0] B,
|
|
output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
|
|
|
|
logic [2**width-1:0] operand;
|
|
always_comb begin
|
|
// A + (sub) ? B : -B
|
|
// Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
|
|
operand = (B ^ {(width){op}});
|
|
{COUT, OUT_1} = A + operand + {{(width-1){1'b0}}, op};
|
|
end
|
|
|
|
// Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
|
|
// Cin for width-2'th bit to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
|
|
assign OUT_CIN = A[width-1] ^ operand[width-1] ^ OUT_1[width-1];
|
|
endmodule
|