77 lines
2.6 KiB
Systemverilog
77 lines
2.6 KiB
Systemverilog
`include "shifter.sv"
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module shifter_tb #(width=8)();
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logic [2:0] op;
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logic [width-1:0] Y;
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logic [width-1:0] A_in;
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logic [$clog2(width)-1:0] B_in;
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logic [width-1:0] C_in;
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logic [2:0] ops[6];
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logic [width-1:0] A[6];
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logic [$clog2(width)-1:0] B[6];
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logic [width-1:0] C[6];
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logic [width-1:0] Y_exp[6];
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shifter #(width) dut(op, A_in,C_in,B_in,Y);
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integer error_count;
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initial begin
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// Test left shift by C
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ops[0] = 3'b000;
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A[0] = {{(width-1){1'b0}}, {1'b1}};
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C[0] = {{(width-1){1'b0}}, {1'b1}};
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B[0] = {width{1'b0}};
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Y_exp[0] = {{(width-2){1'b0}}, {2'b10}};
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// Test left shift by B
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ops[1] = 3'b100;
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A[1] = {{(width-1){1'b0}}, {1'b1}};
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C[1] = {{(width-1){1'b0}}, {1'b1}};
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B[1] = {{($clog2(width)-2){1'b0}}, 2'b10};
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Y_exp[1] = {{(width-3){1'b0}}, {3'b100}};
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// Test Logical right shift by C
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ops[2] = 3'b001;
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A[2] = {{(width-2){1'b0}}, {2'b10}};
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C[2] = {{(width-1){1'b0}}, {1'b1}};
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B[2] = {width{1'b0}};
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Y_exp[2] = {{(width-1){1'b0}}, {1'b1}};
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// Test Logical right shift by B
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ops[3] = 3'b101;
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A[3] = {{(width-1){1'b0}}, {2'b10}};
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C[3] = {{(width-1){1'b0}}, {1'b1}};
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B[3] = {{($clog2(width)-2){1'b0}}, 2'b10};
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Y_exp[3] = {{(width-1){1'b0}}, {1'b0}};
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// Test arithmetic shift right by C
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ops[4] = 3'b011;
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A[4] = {{(width-1){1'b1}}, 1'b0}; // -2
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C[4] = {{(width-1){1'b0}}, 1'b1}; // 1
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B[4] = {{(width-2){1'b0}}, 2'b10}; // 2
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Y_exp[4] = {width{1'b1}}; // -1
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// Test arithmetic shift right by B
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ops[5] = 3'b111;
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A[5] = {{(width-2){1'b1}}, 2'b00}; // -4
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C[5] = {{(width-1){1'b0}}, 1'b1}; // 1
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B[5] = {{(width-2){1'b0}}, 2'b10}; // 2
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Y_exp[5] = {width{1'b1}}; // -1
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error_count = 0;
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$display("Beginning Shifter tests");
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for (integer N = 0; N < $size(ops); ++N) begin
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op = ops[N];
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A_in = A[N];
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B_in = B[N];
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C_in = C[N];
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#1;
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if (Y != Y_exp[N]) begin
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$display("\t\x1b[38;5;9mShifter(%0d) Op 0b%b(0b%b, 0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", N, op, A_in, B_in, C_in, Y, Y_exp[N]);
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error_count = error_count + 1;
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end
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end
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if (error_count == 0) $display("\x1b[38;5;10mAll Shifter tests passing\x1b[m");
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else $display("\x1b[38;5;9m%0d Shifter test(s) failing\x1b[m", error_count);
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end
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endmodule |