33 lines
708 B
Systemverilog
33 lines
708 B
Systemverilog
`ifndef ASS_2_SV
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`define ASS_2_SV
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`ifdef SYNTHESIS
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`include "../../rom.sv"
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`include "../../ram.sv"
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`include "../../instruction_counter.sv"
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`include "../../instruction_classifier.sv"
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`include "../../alu.sv"
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`else
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`include "rom.sv"
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`include "ram.sv"
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`include "instruction_counter.sv"
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`include "instruction_classifier.sv"
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`include "alu.sv"
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`endif
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module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
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logic [romsz-1:0] pc_addr;
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logic [0:0] pc_we;
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logic [2**width-1:0] instruction;
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instruction_counter pc #(romsz)(clk, pc_we, pc_addr, pc_addr);
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ROM rom #(romsz, 2**width)();
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RAM ram #(ramsz, 2**width)();
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alu alu #(width)();
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endmodule
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`endif |