74 lines
3.9 KiB
Plaintext
74 lines
3.9 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2025 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and any partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, the Altera Quartus Prime License Agreement,
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# the Altera IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Altera and sold by Altera or its authorized distributors. Please
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# refer to the Altera Software License Subscription Agreements
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# on the Quartus Prime software download page.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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# Date created = 16:08:41 September 03, 2026
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# seven_seg_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Intel recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone V"
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set_global_assignment -name DEVICE 5CGXFC5C6F27C7
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set_global_assignment -name TOP_LEVEL_ENTITY seven_seg
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:08:41 SEPTEMBER 03, 2026"
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set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition"
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set_global_assignment -name SYSTEMVERILOG_FILE seven_seg.sv
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)"
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_location_assignment PIN_F7 -to segments[0]
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set_location_assignment PIN_V19 -to segments[1]
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set_location_assignment PIN_V18 -to segments[2]
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set_location_assignment PIN_V17 -to segments[3]
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set_location_assignment PIN_W18 -to segments[4]
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set_location_assignment PIN_Y20 -to segments[5]
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set_location_assignment PIN_Y19 -to segments[6]
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set_location_assignment PIN_Y18 -to segments[7]
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set_location_assignment PIN_AC9 -to num[0]
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set_location_assignment PIN_AE10 -to num[1]
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set_location_assignment PIN_AD13 -to num[2]
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set_location_assignment PIN_AC8 -to num[3]
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set_location_assignment PIN_AE19 -to rbi_inv[0]
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |