28 lines
685 B
Systemverilog
28 lines
685 B
Systemverilog
`ifndef CONTROL_UNIT_H
|
|
`define CONTROL_UNIT_H
|
|
`include "instruction_classifier.sv"
|
|
|
|
module control_unit (
|
|
input logic [5:0] op, input logic [5:0] func,
|
|
output logic [0:0] M2R, output logic [0:0] M2W,
|
|
output logic [0:0] B,
|
|
output logic [3:0] ALU_FN, output logic [0:0] ALU_SRC,
|
|
output logic [0:0] RDST, output logic [0:0] RW
|
|
);
|
|
logic [0:0] TYPE_R;
|
|
logic [0:0] TYPE_B1;
|
|
logic [0:0] TYPE_J;
|
|
logic [0:0] TYPE_B2;
|
|
logic [0:0] TYPE_I;
|
|
logic [0:0] TYPE_F;
|
|
logic [0:0] TYPE_M;
|
|
|
|
instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);
|
|
|
|
always_comb begin
|
|
// TODO
|
|
end
|
|
|
|
endmodule
|
|
`endif
|