18 lines
462 B
Systemverilog
18 lines
462 B
Systemverilog
`ifndef INSTRUCTION_CLASSIFIER_H_SV
|
|
`define INSTRUCTION_CLASSIFIER_H_SV
|
|
|
|
module instruction_module_classifier(
|
|
input logic [2:0] op,
|
|
output logic en_shifter,
|
|
output logic en_jmp,
|
|
output logic en_mul,
|
|
output logic en_alu,
|
|
);
|
|
always_comb begin
|
|
en_shifter = (op & 3'b111) == 3'b000;
|
|
en_jmp = (op & 3'b111) == 3'b001;
|
|
en_mul = (op & 3'b110) == 3'b010;
|
|
en_alu = (op & 3'b100) == 3'b100;
|
|
end
|
|
endmodule
|
|
`endif |