53 lines
1.5 KiB
Systemverilog
53 lines
1.5 KiB
Systemverilog
`include "rom.sv"
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`include "ram.sv"
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`include "register_file.sv"
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`include "instruction_counter.sv"
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`include "instruction_classifier.sv"
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`include "instruction_module_classifier.sv"
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`include "alu.sv"
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`include "shifter.sv"
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module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
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logic [romsz-1:0] pc_addr;
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logic [romsz-1:0] pc_addr_write;
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logic [0:0] pc_we;
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logic [2**width-1:0] instruction;
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logic[0:0] R;
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logic[0:0] B1;
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logic[0:0] J;
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logic[0:0] B2;
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logic[0:0] I;
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logic[0:0] F;
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logic[0:0] M;
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logic [0:0] en_shifter;
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logic [0:0] en_jmp;
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logic [0:0] en_mul;
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logic [0:0] en_alu;
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logic [1:0] flags;
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logic [2**width-1:0] rs;
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logic [2**width-1:0] rt;
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logic [2**width-1:0] rd;
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logic [0:0] rd_we;
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instruction_counter PC #(romsz)(clk, pc_we, pc_addr, pc_addr_write);
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rom ROM #(romsz, 2**width)(pc_addr, instruction);
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instruction_classifier INSTRUCTION_CLASSIFIER(instruction[31:26], R, B1, J, B2, I, F, M);
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instruction_module_classifier INSTRUCTION_MODULE_CLASSIFIER(instruction[5:3], en_shifter, en_jmp, en_mul, en_alu);
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register_file REGS #(width, 32)(clk,
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rd_we, instruction[15:11],
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rs, instruction[25:21],
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rt, instruction[20:16]
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);
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logic [2**width-1:0] rd_alu;
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alu ALU #(width)(instruction[3:0], rs, rt, rd_alu, flags[1:0]);
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logic [2**width-1:0] rd_shifter;
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shifter SHIFTER #(width)(instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter);
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endmodule |