16 lines
427 B
Systemverilog
16 lines
427 B
Systemverilog
module gatereg #(width)(
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input logic [0:0] clk, input logic [0:0] rst, input logic en[0:0],
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input logic [2**width-1:0] in, output logic [2**width-1:0] out
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);
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logic [2**width-1:0] hold_value;
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assign out = hold_value;
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always_ff @( posedge clk ) begin
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if (rst) begin
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hold_value <= {(2**width){0}};
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end else if (en) begin
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hold_value <= in;
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end
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end
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endmodule |