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FPGA_Uni/Quartus/A2/output_files/assignment2.fit.summary
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TroubleElectrical 8b48084fa5 Repaired Sign extender module again to ensure only combinational logic used
(There was a compilation error before, also compiled and tested code on board)
2026-10-22 15:53:15 +11:00

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Fitter Status : Successful - Thu Oct 22 15:47:44 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : assignment2
Top-level Entity Name : assignment2
Family : Cyclone V
Device : 5CGXFC5C6F27C7
Timing Models : Final
Logic utilization (in ALMs) : 5,271 / 29,080 ( 18 % )
Total registers : 9403
Total pins : 41 / 364 ( 11 % )
Total virtual pins : 0
Total block memory bits : 0 / 4,567,040 ( 0 % )
Total RAM Blocks : 0 / 446 ( 0 % )
Total DSP Blocks : 0 / 150 ( 0 % )
Total HSSI RX PCSs : 0 / 6 ( 0 % )
Total HSSI PMA RX Deserializers : 0 / 6 ( 0 % )
Total HSSI TX PCSs : 0 / 6 ( 0 % )
Total HSSI PMA TX Serializers : 0 / 6 ( 0 % )
Total PLLs : 0 / 12 ( 0 % )
Total DLLs : 0 / 4 ( 0 % )