Files
FPGA_Uni/modules/rom.sv
T
TroubleElectrical 25a953cdc6 Added 4 digit 7seg display module (confirmed working for now),
Added Inputs for displaying registers / Program Counter high and low bits,
Assigned pins for Display digits, inputs (Labeled HID) and the clk button
2026-10-13 16:32:15 +11:00

25 lines
628 B
Systemverilog

`ifndef ROM_H
`define ROM_H
module rom #(parameter m=7,p=4) (
input logic [m-1:0] Ad,
output logic [p-1:0] Dout
);
logic [p-1:0] mem[2**m-1:0];
assign Dout = mem[Ad];
//Load the program in memory
// The machine code stored in text file program.dat written in Hex format
initial begin
`ifdef QUARTUS_SYNTH
$readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
`else
$readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
`endif
end
endmodule // end rom module
`endif