Logo
Explore Help
Sign In
TroubleElectrical/FPGA_Uni
Watch 1
Star 0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
Files
ac6c4cc0942924c01de7563b0c99af01b99780f9
FPGA_Uni/Quartus
T
History
TroubleElectrical 80416e1f8a TODO: Remove Shifter Code
2026-10-13 16:57:03 +11:00
..
A1_Q1
Added 4 digit 7seg display module (confirmed working for now),
2026-10-13 16:32:15 +11:00
A1_Q2
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
A1_Q3
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
A1_Q4
Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)
2026-09-15 19:43:28 +10:00
A1_Q5
Implemented instruction classifier on board (Q6) and added blank submission files (for now)
2026-09-15 20:00:35 +10:00
A1_Q6
Updated register_file.sv with proper naming scheme and 32bit width
2026-10-08 15:10:40 +11:00
A2
TODO: Remove Shifter Code
2026-10-13 16:57:03 +11:00
Powered by Gitea Version: 28.3.0 Page: 79ms Template: 6ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API