20 lines
596 B
Systemverilog
20 lines
596 B
Systemverilog
`include "asu.sv"
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`include "lu.sv"
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// flags[0:0] = Cout
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// flags[1:1] = Overflow
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module alu #(parameter width=2)(input logic [3:0] op,
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input logic [2**width-1:0] A, input logic [2**width-1:0] B,
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output logic [2**width-1:0] OUT_1, output logic flags[1:0]);
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logic [2**width-1:0] asu_out;
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logic [1:0] asu_flags;
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logic [0:0] asu_op;
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asu #(width) adder_unit(asu_op, A, B, asu_out, asu_flags[0], asu_flags[1]);
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logic [width-1:0] lu_out;
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lu #(width) logic_unit(op[1:0], A, B, lu_out);
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// Cout = asu_flags[0]
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// Overflow = asu_flags[0] ^ asu_flags[1]
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endmodule |