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FPGA_Uni/Quartus/A1_Q4/db/alu.hier_info
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|alu
op[0] => op[0].IN1
op[1] => op[1].IN1
op[2] => Mux0.IN3
op[2] => Mux1.IN3
op[2] => Mux2.IN3
op[2] => Mux3.IN9
op[3] => Mux0.IN2
op[3] => Mux1.IN2
op[3] => Mux2.IN2
op[3] => Mux3.IN8
A[0] => A[0].IN2
A[1] => A[1].IN2
A[2] => A[2].IN2
A[3] => A[3].IN2
B[0] => B[0].IN2
B[1] => B[1].IN2
B[2] => B[2].IN2
B[3] => B[3].IN2
OUT_1[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
flags[0] <= asu:adder_unit.port4
flags[1] <= asu:adder_unit.port5
|alu|asu:adder_unit
op[0] => operand[3].OUTPUTSELECT
op[0] => operand[2].OUTPUTSELECT
op[0] => operand[1].OUTPUTSELECT
op[0] => operand[0].OUTPUTSELECT
op[0] => _.DATAB
A[0] => _.DATAD
A[1] => _.DATAD
A[2] => _.DATAD
A[3] => OUT_CIN.IN1
A[3] => _.DATAD
B[0] => operand[0].DATAB
B[0] => operand[0].DATAA
B[1] => operand[1].DATAB
B[1] => operand[1].DATAA
B[2] => operand[2].DATAB
B[2] => operand[2].DATAA
B[3] => operand[3].DATAB
B[3] => operand[3].DATAA
OUT_1[0] <= _.SUM_OUT
OUT_1[1] <= _.SUM_OUT
OUT_1[2] <= _.SUM_OUT
OUT_1[3] <= _.SUM_OUT
COUT[0] <= _.SUM_OUT
OUT_CIN[0] <= OUT_CIN.DB_MAX_OUTPUT_PORT_TYPE
|alu|lu:logic_unit
op[0] => Mux0.IN5
op[0] => Mux1.IN5
op[0] => Mux2.IN5
op[0] => Mux3.IN5
op[1] => Mux0.IN4
op[1] => Mux1.IN4
op[1] => Mux2.IN4
op[1] => Mux3.IN4
A[0] => Y.IN0
A[0] => Y.IN0
A[0] => Y.IN0
A[1] => Y.IN0
A[1] => Y.IN0
A[1] => Y.IN0
A[2] => Y.IN0
A[2] => Y.IN0
A[2] => Y.IN0
A[3] => Y.IN0
A[3] => Y.IN0
A[3] => Y.IN0
B[0] => Y.IN1
B[0] => Y.IN1
B[0] => Y.IN1
B[1] => Y.IN1
B[1] => Y.IN1
B[1] => Y.IN1
B[2] => Y.IN1
B[2] => Y.IN1
B[2] => Y.IN1
B[3] => Y.IN1
B[3] => Y.IN1
B[3] => Y.IN1
Y[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
Y[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
Y[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
Y[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE