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9e5fb6f52b50bb1d56b14554611f4ffa5ed384a0
FPGA_Uni
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Quartus
T
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TroubleElectrical
9e5fb6f52b
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
..
A1_Q1
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
A1_Q2
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
A1_Q3
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
A1_Q4
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
A1_Q5
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
A1_Q6
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
