#      $File: NewcastleUniversity/ELEC4720/2026s2/src/Code/Assignment/Ass-02-Demo.s $
#      $Date: 2026-10-07 01:54:03 +1100 (Wed, 07 Oct 2026) $
#  $Revision: 2525 $
#    $Author: Peter $
#
#     Course: ELEC4720(2026s2) Programmable Logic Design
#     School: Engineering
# University: The University of Newcastle
#    Address: CALLAGHAN NSW 2308 Australia
#
#     Author: Dr Peter Stepien
#      Email: peter.stepien@newcastle.edu.au
#  Copyright: 2026
	
# Assignment 2 Demonstration Program (all instructions)

	.text
	.globl main
	.globl loop
	.globl finish

main:
	# Initialise some registers
	subu $t0, $t0, $t0 # Set t0 = 0 (R8, modified below)
	addiu $t1, $t0, 7  # Set t1 = 7 (R9)

	# Memory operations
	sw $t1, 0x10000000($t0) # Save t1 to memory (change to 0x0000 for FPGA)
	lw $t2, 0x10000000($t0) # Load t2 from memory (change to 0x0000 for FPGA) (R10)
	
	# Remaining arithmetic
	addu $t3, $t1, $t2 # Unsigned t3 = t1 + t2 = 14 (R11)
	sub $t4, $t1, $t3  # Signed   t4 = t1 - t3 = -7 (R12)
	addi $t5, $t1, 3   # Signed   t5 = t1 +  3 = 10 (R13)
	add $t6, $t4, $t5  # Signed   t6 = t4 + t5 =  3 (R14)

	# Logical (t1 = 0000..0111, t5 = 0000..1010)
	and $s0, $t1, $t5  # s0 = t1 and t5 =   2 (0000..0010) (R16)
	or $s1, $t1, $t5   # s1 = t1 or  t5 =  15 (0000..1111) (R17)
	xor $s2, $t1, $t5  # s2 = t1 xor t5 =  13 (0000..1101) (R18)
	nor $s3, $t1, $t5  # s3 = t1 nor t5 = -16 (1111..0000) (R19)

	# Comparison
	slt $s4, $t4, $t6  # Signed   s4 = t4 < t6 = 1 (true)  (R20)
	sltu $s5, $t4, $t6 # Unsigned s5 = t4 < t6 = 0 (false) (R21)

	# Loop to test branch
loop:
	addiu $t0, $t0, 1  # Increment counter
	sltu $s6, $t0, $t5 # Unsigned s6 = t0 < t5 (Last 0) (R22)
	beq $s6, $s4, loop # Loop if s6 == s4

    # Endless loop at end of program (FPGA)
finish:
    # beq $s6, $s6, finish # Endless loop
    
    # Alternative system call to exit program (spim)
	li $v0, 10
	syscall

# END OF FILE