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9583abd3073b2cab2c71b5b5b4e6f9ce15f5754e
FPGA_Uni
/
Quartus
/
A1_Q5
T
History
TroubleElectrical
9583abd307
Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)
2026-09-15 19:43:28 +10:00
..
db
Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)
2026-09-15 19:43:28 +10:00
incremental_db
Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)
2026-09-15 19:43:28 +10:00
output_files
Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)
2026-09-15 19:43:28 +10:00
simulation
/questa
Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)
2026-09-15 19:43:28 +10:00
A1_Q5.qpf
Added projects for A1 q2 to q6
2026-09-04 13:12:33 +10:00
c5_pin_model_dump.txt
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
shifter.qsf
Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)
2026-09-15 19:43:28 +10:00