TroubleElectrical 9583abd307 Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)

2026-09-15 19:43:28 +10:00

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A1_Q1

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

A1_Q2

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

A1_Q3

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

A1_Q4

Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)

2026-09-15 19:43:28 +10:00

A1_Q5

Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)

2026-09-15 19:43:28 +10:00

A1_Q6

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00