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9583abd3073b2cab2c71b5b5b4e6f9ce15f5754e
FPGA_Uni
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Quartus
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A1_Q3
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output_files
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asu.done
T
TroubleElectrical
9e5fb6f52b
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
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Tue Sep 15 16:40:10 2026
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