riley
92a0cb17da
Added a QUARTUS_SYNTH around the display logic at the end of the module. Partially fixed control_unit module, still seems to need some changes as branching doesn't appear to work at all.
105 lines
2.5 KiB
Systemverilog
105 lines
2.5 KiB
Systemverilog
`ifndef ASS_2_SV
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`define ASS_2_SV
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`include "rom.sv"
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`include "ram.sv"
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`include "register_file.sv"
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`include "instruction_counter.sv"
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`include "control_unit.sv"
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`include "alu.sv"
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`include "shifter.sv"
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`include "sign_extender.sv"
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`include "seven_seg_4digit.sv"
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module assignment2 #(width=5, ramsz=9, romsz=10) (
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input logic [0:0] clk
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`ifdef QUARTUS_SYNTH
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,
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input logic [4:0] HID_Register,
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input logic [0:0] HID_PC,
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input logic [0:0] HID_Hi_Low,
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output logic[7:0] out_seg_0,
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output logic[7:0] out_seg_1,
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output logic[7:0] out_seg_2,
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output logic[7:0] out_seg_3
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`endif
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);
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// Intermediate for displaying high / low of PC or Register
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logic[15:0] PC_Reg_Display;
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// Program / Instruction Counter Intermediates
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logic [2**width-1:0] pc_addr;
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logic [2**width-1:0] pc_addr_write;
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logic [0:0] pc_we;
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logic [2**width-1:0] instruction;
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// Instruction Classifier Intermediates
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logic [0:0] M2R;
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logic [0:0] M2W;
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logic [0:0] B;
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logic [3:0] ALU_FN;
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logic [0:0] ALU_SRC;
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logic [0:0] RDST;
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logic [0:0] RW;
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// Register File intermediates
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logic [2:0] flags;
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logic [2**width-1:0] rs;
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logic [2**width-1:0] rt;
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logic [2**width-1:0] rd;
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logic [0:0] rd_we;
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logic [31:0] regs_out [32];
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instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
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rom #(romsz, width) ROM (pc_addr, instruction);
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logic [2**width-1:0] rd_mem;
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ram #(ramsz, width) RAM (clk, rd_alu, M2W, rt, rd_mem);
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control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
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M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW
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);
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register_file #(width, 5) REGS (
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clk, rd_we,
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(RDST) ? instruction[15:11] : instruction[20:16], rd,
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instruction[25:21], rs,
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instruction[20:16], rt,
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regs_out
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);
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// Always use sign-extension
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logic [2**width-1:0] rt_imm;
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sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], rt_imm);
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logic [2**width-1:0] rd_alu;
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logic [2**width-1:0] rt_alu;
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alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags);
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assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt);
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assign pc_we = B & flags[2];
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assign pc_addr_write = (rt_imm << 2) + pc_addr;
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assign rd_we = RW;
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assign rd = (M2R) ? rd_mem : rd_alu;
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`ifdef QUARTUS_SYNTH
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// Temporary Test output
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// assign PC_Reg_Display = 16'hC342;
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assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];
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seven_seg_4digit display (
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.num(PC_Reg_Display),
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.segments0(out_seg_0),
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.segments1(out_seg_1),
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.segments2(out_seg_2),
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.segments3(out_seg_3)
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);
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`endif
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endmodule
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`endif
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