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8a682347f0c5b883c4195f1a5f454c73cd32fd26
FPGA_Uni
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ModelSim
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TroubleElectrical
5d9e7f541e
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
..
_info
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
_lib1_12.qdb
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
_lib1_12.qpg
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
_lib1_12.qtl
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
_lib.qdb
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
_vmake
Added ModelSim folder (and have to add files into it as to allow for different testbench code)
2026-09-08 16:32:01 +10:00