TroubleElectrical c27a04ef73 Implemented instruction classifier on board (Q6) and added blank submission files (for now)

2026-09-15 20:00:35 +10:00

..

shifter.db_info

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

shifter.root_partition.cmp.ammdb

Implemented instruction classifier on board (Q6) and added blank submission files (for now)

2026-09-15 20:00:35 +10:00

shifter.root_partition.cmp.cdb

Implemented instruction classifier on board (Q6) and added blank submission files (for now)

2026-09-15 20:00:35 +10:00

shifter.root_partition.cmp.dfp

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

shifter.root_partition.cmp.hbdb.cdb

Implemented instruction classifier on board (Q6) and added blank submission files (for now)

2026-09-15 20:00:35 +10:00

shifter.root_partition.cmp.hbdb.hdb

Implemented instruction classifier on board (Q6) and added blank submission files (for now)

2026-09-15 20:00:35 +10:00

shifter.root_partition.cmp.hbdb.sig

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

shifter.root_partition.cmp.hdb

Implemented instruction classifier on board (Q6) and added blank submission files (for now)

2026-09-15 20:00:35 +10:00

shifter.root_partition.cmp.logdb

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

shifter.root_partition.cmp.rcfdb

Implemented instruction classifier on board (Q6) and added blank submission files (for now)

2026-09-15 20:00:35 +10:00

shifter.root_partition.map.cdb

Implemented instruction classifier on board (Q6) and added blank submission files (for now)

2026-09-15 20:00:35 +10:00

shifter.root_partition.map.dpi

Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)

2026-09-15 19:43:28 +10:00

shifter.root_partition.map.hbdb.cdb

Implemented instruction classifier on board (Q6) and added blank submission files (for now)

2026-09-15 20:00:35 +10:00

shifter.root_partition.map.hbdb.hb_info

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

shifter.root_partition.map.hbdb.hdb

Implemented instruction classifier on board (Q6) and added blank submission files (for now)

2026-09-15 20:00:35 +10:00

shifter.root_partition.map.hbdb.sig

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

shifter.root_partition.map.hdb

Implemented instruction classifier on board (Q6) and added blank submission files (for now)

2026-09-15 20:00:35 +10:00

shifter.root_partition.map.kpt

Added all Testbenches to Modelsim and confirmed working operation

2026-09-15 15:15:00 +10:00

shifter.rrp.hdb

Implemented instruction classifier on board (Q6) and added blank submission files (for now)

2026-09-15 20:00:35 +10:00

shifter.rrs.cdb

Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)

2026-09-15 19:43:28 +10:00