Files
FPGA_Uni/modules/sign_extender.sv
T
TroubleElectrical 8b48084fa5 Repaired Sign extender module again to ensure only combinational logic used
(There was a compilation error before, also compiled and tested code on board)
2026-10-22 15:53:15 +11:00

17 lines
434 B
Systemverilog

`ifndef SIGN_EXTENDER_H
`define SIGN_EXTENDER_H
module sign_extender #(in_width=4, out_width=5)(
input logic [0:0] op,
input logic [2**in_width-1:0] val,
output logic [2**out_width-1:0] ext_val
);
logic [0:0] msb;
assign msb = (val >> (in_width-1)) & 1'b1;
assign ext_val = op
? { {(2**out_width - 2**in_width){msb}}, val }
: { {(2**out_width - 2**in_width){1'b0}}, val };
endmodule
`endif