TroubleElectrical
25a953cdc6
Added Inputs for displaying registers / Program Counter high and low bits, Assigned pins for Display digits, inputs (Labeled HID) and the clk button
45 lines
833 B
Systemverilog
45 lines
833 B
Systemverilog
`ifndef SEVEN_SEG_4_H_SV
|
|
`define SEVEN_SEG_4_H_SV
|
|
|
|
`include "seven_seg.sv"
|
|
module seven_seg_4digit (
|
|
input logic [15:0] num,
|
|
output logic [7:0] segments0,
|
|
output logic [7:0] segments1,
|
|
output logic [7:0] segments2,
|
|
output logic [7:0] segments3
|
|
);
|
|
|
|
// Rightmost digit
|
|
seven_seg digit0 (
|
|
.num(num[3:0]),
|
|
.rbi_inv(1'b0),
|
|
.segments(segments0)
|
|
);
|
|
|
|
// Second digit from right
|
|
seven_seg digit1 (
|
|
.num(num[7:4]),
|
|
.rbi_inv(1'b0),
|
|
.segments(segments1)
|
|
);
|
|
|
|
// Third digit from right
|
|
seven_seg digit2 (
|
|
.num(num[11:8]),
|
|
.rbi_inv(1'b0),
|
|
.segments(segments2)
|
|
);
|
|
|
|
// Leftmost digit
|
|
seven_seg digit3 (
|
|
.num(num[15:12]),
|
|
.rbi_inv(1'b0),
|
|
.segments(segments3)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`endif
|
|
|