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FPGA_Uni
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5acf1c8b87db2510c0d91ca308406a17478bed34
FPGA_Uni
/
Quartus
/
A1_Q2
T
History
TroubleElectrical
60e5dae43b
Added ModelSim folder (and have to add files into it as to allow for different testbench code)
2026-09-08 16:32:01 +10:00
..
db
Added ModelSim folder (and have to add files into it as to allow for different testbench code)
2026-09-08 16:32:01 +10:00
incremental_db
Added ModelSim folder (and have to add files into it as to allow for different testbench code)
2026-09-08 16:32:01 +10:00
output_files
Added ModelSim folder (and have to add files into it as to allow for different testbench code)
2026-09-08 16:32:01 +10:00
simulation
/questa
Added ModelSim folder (and have to add files into it as to allow for different testbench code)
2026-09-08 16:32:01 +10:00
A1_Q2.qpf
Added projects for A1 q2 to q6
2026-09-04 13:12:33 +10:00
c5_pin_model_dump.txt
Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.
2026-09-08 15:36:51 +10:00
lu.qsf
Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.
2026-09-08 15:36:51 +10:00
lu.qws
Added ModelSim folder (and have to add files into it as to allow for different testbench code)
2026-09-08 16:32:01 +10:00