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FPGA_Uni/Quartus/A1_Q4/db
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TroubleElectrical 9583abd307 Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)
2026-09-15 19:43:28 +10:00
..
.cmp.kpt
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
A1_Q4.map_bb.logdb
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
alu_partition_pins.json
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.(0).cnf.cdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.(0).cnf.hdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.(1).cnf.cdb
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
alu.(1).cnf.hdb
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
alu.(2).cnf.cdb
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
alu.(2).cnf.hdb
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
alu.(3).cnf.cdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.(3).cnf.hdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.(4).cnf.cdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.(4).cnf.hdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.(5).cnf.cdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.(5).cnf.hdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.(6).cnf.cdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.(6).cnf.hdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.(7).cnf.cdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.(7).cnf.hdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.(8).cnf.cdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.(8).cnf.hdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.asm.qmsg
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.asm.rdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.cbx.xml
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
alu.cmp_merge.kpt
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
alu.cmp.bpm
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.cmp.cdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.cmp.hdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.cmp.idb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.cmp.logdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.cmp.rdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.cyclonev_io_sim_cache.ff_0c_fast.hsd
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
alu.cyclonev_io_sim_cache.ff_85c_fast.hsd
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
alu.cyclonev_io_sim_cache.ii_0c_slow.hsd
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
alu.cyclonev_io_sim_cache.ii_85c_slow.hsd
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
alu.db_info
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.eda.qmsg
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.fit.qmsg
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.hier_info
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.hif
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.lpc.html
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.lpc.rdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.lpc.txt
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.map_bb.cdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.map_bb.hdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.map.ammdb
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
alu.map.bpm
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.map.cdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.map.hdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.map.kpt
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
alu.map.qmsg
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.map.rdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.pplq.rdb
Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)
2026-09-15 19:43:28 +10:00
alu.pre_map.hdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.root_partition.map.reg_db.cdb
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
alu.routing.rdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.rtlv_sg_swap.cdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.rtlv_sg.cdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.rtlv.hdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.sld_design_entry_dsc.sci
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
alu.sld_design_entry.sci
Added projects for A1 q2 to q6
2026-09-04 13:12:33 +10:00
alu.smart_action.txt
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
alu.sta_cmp.7_H6_slow_1100mv_85c.tdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.sta.qmsg
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.sta.rdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.tis_db_list.ddb
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
alu.tiscmp.fast_1100mv_0c.ddb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.tiscmp.fast_1100mv_85c.ddb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.tiscmp.fastest_slow_1100mv_0c.ddb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.tiscmp.fastest_slow_1100mv_85c.ddb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.tiscmp.slow_1100mv_0c.ddb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.tiscmp.slow_1100mv_85c.ddb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.tmw_info
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
alu.vpr.ammdb
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
prev_cmp_A1_Q4.qmsg
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00