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FPGA_Uni
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392f1f7a275620e0073281613842f03294871b86
FPGA_Uni
/
Quartus
/
A1_Q1
/
simulation
/
questa
T
History
TroubleElectrical
9e5fb6f52b
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
..
seven_seg.sft
Including quartus prime lite edition project folders for flashing the project to the board
2026-09-03 16:34:31 +10:00
seven_seg.svo
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
