52 lines
1.3 KiB
Plaintext
52 lines
1.3 KiB
Plaintext
// $File: NewcastleUniversity/ELEC4720/2026s2/src/Code/Assignment/Ass-03-HazardsDemo.txt $
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// $Date: 2026-10-29 14:44:32 +1100 (Thu, 29 Oct 2026) $
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// $Revision: 2531 $
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// $Author: Peter $
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//
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// Course: ELEC4720(2026s2) Programmable Logic Design
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// School: Engineering
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// University: The University of Newcastle
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// Address: CALLAGHAN NSW 2308 Australia
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//
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// Author: Dr Peter Stepien
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// Email: peter.stepien@newcastle.edu.au
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// Copyright: 2026
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// Assignment 3 Demonstration Program (with hazards)
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// main:
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// Initialise some registers
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01084023 // subu $t0, $t0, $t0
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25090007 // addiu $t1, $t0, 7
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// Memory operations
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ad090000 // sw $t1, 0x0000($t0)
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8d0a0000 // lw $t2, 0x0000($t0)
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// Remaining arithmetic
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012a5821 // addu $t3, $t1, $t2
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012b6022 // sub $t4, $t1, $t3
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212d0003 // addi $t5, $t1, 3
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018d7020 // add $t6, $t4, $t5
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// Logical
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012d8024 // and $s0, $t1, $t5
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012d8825 // or $s1, $t1, $t5
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012d9026 // xor $s2, $t1, $t5
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012d9827 // nor $s3, $t1, $t5
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// Comparison
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018ea02a // slt $s4, $t4, $t6
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018ea82b // sltu $s5, $t4, $t6
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// Loop to test branch
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// loop:
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25080001 // addiu $t0, $t0, 1
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010db02b // sltu $s6, $t0, $t5
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12d4fffd // beq $s6, $s4, loop
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// Endless loop at end of program (FPGA)
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// finish:
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12d6ffff // beq $s6, $s6, finish
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