riley 5acf1c8b87 Fixed bug in adder/subtracter where code assuming width was the bit width was not updated when moving to the 2**N approach required by the assignment. Updated adder/subtracter testbench to correctly instantiate the asser/subtracter and removed unused variable

2026-09-08 22:49:22 +10:00

..

alu_tb.sv

Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage

2026-09-03 16:32:56 +10:00

asu_tb.sv

Fixed bug in adder/subtracter where code assuming width was the bit width was not updated when moving to the 2**N approach required by the assignment. Updated adder/subtracter testbench to correctly instantiate the asser/subtracter and removed unused variable

2026-09-08 22:49:22 +10:00

instruction_classifier_tb.sv

Removed debug statement from instruction classifier testbench

2026-09-08 21:44:36 +10:00

lu_tb.sv

Fixed error in logic unit testbench where it didn't instansiate the DUT at all as well as some faulty test cases and reset logic

2026-09-08 22:00:07 +10:00

lu_tb.sv.bak

Added ModelSim folder (and have to add files into it as to allow for different testbench code)

2026-09-08 16:32:01 +10:00

seven_seg_tb.sv

Updated seven segment test bench to reflect prior commit

2026-09-03 16:58:11 +10:00

shifter_tb.sv

Implemented shifter and its test bench code fully

2026-09-08 22:35:14 +10:00

tests.sv

Implemented shifter and its test bench code fully

2026-09-08 22:35:14 +10:00