385 lines
11 KiB
Plaintext
385 lines
11 KiB
Plaintext
// Copyright (C) 2025 Altera Corporation. All rights reserved.
|
|
// Your use of Altera Corporation's design tools, logic functions
|
|
// and other software and tools, and any partner logic
|
|
// functions, and any output files from any of the foregoing
|
|
// (including device programming or simulation files), and any
|
|
// associated documentation or information are expressly subject
|
|
// to the terms and conditions of the Altera Program License
|
|
// Subscription Agreement, the Altera Quartus Prime License Agreement,
|
|
// the Altera IP License Agreement, or other applicable license
|
|
// agreement, including, without limitation, that your use is for
|
|
// the sole purpose of programming logic devices manufactured by
|
|
// Altera and sold by Altera or its authorized distributors. Please
|
|
// refer to the Altera Software License Subscription Agreements
|
|
// on the Quartus Prime software download page.
|
|
|
|
// VENDOR "Altera"
|
|
// PROGRAM "Quartus Prime"
|
|
// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
|
|
|
|
// DATE "09/08/2026 15:26:13"
|
|
|
|
//
|
|
// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
|
|
//
|
|
|
|
//
|
|
// This Verilog file should be used for Questa Altera FPGA (SystemVerilog) only
|
|
//
|
|
|
|
`timescale 1 ps/ 1 ps
|
|
|
|
module lu (
|
|
op,
|
|
A,
|
|
B,
|
|
Y);
|
|
input [1:0] op;
|
|
input [3:0] A;
|
|
input [3:0] B;
|
|
output [3:0] Y;
|
|
|
|
// Design Ports Information
|
|
// Y[0] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default
|
|
// Y[1] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default
|
|
// Y[2] => Location: PIN_G6, I/O Standard: 2.5 V, Current Strength: Default
|
|
// Y[3] => Location: PIN_G7, I/O Standard: 2.5 V, Current Strength: Default
|
|
// A[0] => Location: PIN_AC9, I/O Standard: 1.2 V, Current Strength: Default
|
|
// B[0] => Location: PIN_W11, I/O Standard: 1.2 V, Current Strength: Default
|
|
// op[0] => Location: PIN_Y11, I/O Standard: 1.2 V, Current Strength: Default
|
|
// op[1] => Location: PIN_AE19, I/O Standard: 1.2 V, Current Strength: Default
|
|
// A[1] => Location: PIN_AE10, I/O Standard: 1.2 V, Current Strength: Default
|
|
// B[1] => Location: PIN_AB10, I/O Standard: 1.2 V, Current Strength: Default
|
|
// A[2] => Location: PIN_AD13, I/O Standard: 1.2 V, Current Strength: Default
|
|
// B[2] => Location: PIN_V10, I/O Standard: 1.2 V, Current Strength: Default
|
|
// A[3] => Location: PIN_AC8, I/O Standard: 1.2 V, Current Strength: Default
|
|
// B[3] => Location: PIN_AC10, I/O Standard: 1.2 V, Current Strength: Default
|
|
|
|
|
|
wire gnd;
|
|
wire vcc;
|
|
wire unknown;
|
|
|
|
assign gnd = 1'b0;
|
|
assign vcc = 1'b1;
|
|
assign unknown = 1'bx;
|
|
|
|
tri1 devclrn;
|
|
tri1 devpor;
|
|
tri1 devoe;
|
|
wire \~QUARTUS_CREATED_GND~I_combout ;
|
|
wire \B[0]~input_o ;
|
|
wire \A[0]~input_o ;
|
|
wire \op[0]~input_o ;
|
|
wire \op[1]~input_o ;
|
|
wire \Mux3~0_combout ;
|
|
wire \A[1]~input_o ;
|
|
wire \B[1]~input_o ;
|
|
wire \Mux2~0_combout ;
|
|
wire \B[2]~input_o ;
|
|
wire \A[2]~input_o ;
|
|
wire \Mux1~0_combout ;
|
|
wire \A[3]~input_o ;
|
|
wire \B[3]~input_o ;
|
|
wire \Mux0~0_combout ;
|
|
|
|
|
|
// Location: IOOBUF_X14_Y61_N53
|
|
cyclonev_io_obuf \Y[0]~output (
|
|
.i(\Mux3~0_combout ),
|
|
.oe(vcc),
|
|
.dynamicterminationcontrol(gnd),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.parallelterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(Y[0]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \Y[0]~output .bus_hold = "false";
|
|
defparam \Y[0]~output .open_drain_output = "false";
|
|
defparam \Y[0]~output .shift_series_termination_control = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X15_Y61_N36
|
|
cyclonev_io_obuf \Y[1]~output (
|
|
.i(\Mux2~0_combout ),
|
|
.oe(vcc),
|
|
.dynamicterminationcontrol(gnd),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.parallelterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(Y[1]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \Y[1]~output .bus_hold = "false";
|
|
defparam \Y[1]~output .open_drain_output = "false";
|
|
defparam \Y[1]~output .shift_series_termination_control = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X15_Y61_N53
|
|
cyclonev_io_obuf \Y[2]~output (
|
|
.i(\Mux1~0_combout ),
|
|
.oe(vcc),
|
|
.dynamicterminationcontrol(gnd),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.parallelterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(Y[2]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \Y[2]~output .bus_hold = "false";
|
|
defparam \Y[2]~output .open_drain_output = "false";
|
|
defparam \Y[2]~output .shift_series_termination_control = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X14_Y61_N36
|
|
cyclonev_io_obuf \Y[3]~output (
|
|
.i(\Mux0~0_combout ),
|
|
.oe(vcc),
|
|
.dynamicterminationcontrol(gnd),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.parallelterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(Y[3]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \Y[3]~output .bus_hold = "false";
|
|
defparam \Y[3]~output .open_drain_output = "false";
|
|
defparam \Y[3]~output .shift_series_termination_control = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X10_Y0_N41
|
|
cyclonev_io_ibuf \B[0]~input (
|
|
.i(B[0]),
|
|
.ibar(gnd),
|
|
.dynamicterminationcontrol(gnd),
|
|
.o(\B[0]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \B[0]~input .bus_hold = "false";
|
|
defparam \B[0]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X14_Y0_N35
|
|
cyclonev_io_ibuf \A[0]~input (
|
|
.i(A[0]),
|
|
.ibar(gnd),
|
|
.dynamicterminationcontrol(gnd),
|
|
.o(\A[0]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \A[0]~input .bus_hold = "false";
|
|
defparam \A[0]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X10_Y0_N58
|
|
cyclonev_io_ibuf \op[0]~input (
|
|
.i(op[0]),
|
|
.ibar(gnd),
|
|
.dynamicterminationcontrol(gnd),
|
|
.o(\op[0]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \op[0]~input .bus_hold = "false";
|
|
defparam \op[0]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X50_Y0_N35
|
|
cyclonev_io_ibuf \op[1]~input (
|
|
.i(op[1]),
|
|
.ibar(gnd),
|
|
.dynamicterminationcontrol(gnd),
|
|
.o(\op[1]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \op[1]~input .bus_hold = "false";
|
|
defparam \op[1]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: LABCELL_X17_Y1_N30
|
|
cyclonev_lcell_comb \Mux3~0 (
|
|
// Equation(s):
|
|
// \Mux3~0_combout = ( \op[0]~input_o & ( \op[1]~input_o & ( (!\B[0]~input_o & !\A[0]~input_o ) ) ) ) # ( !\op[0]~input_o & ( \op[1]~input_o & ( !\B[0]~input_o $ (!\A[0]~input_o ) ) ) ) # ( \op[0]~input_o & ( !\op[1]~input_o & ( (\A[0]~input_o ) #
|
|
// (\B[0]~input_o ) ) ) ) # ( !\op[0]~input_o & ( !\op[1]~input_o & ( (\B[0]~input_o & \A[0]~input_o ) ) ) )
|
|
|
|
.dataa(gnd),
|
|
.datab(!\B[0]~input_o ),
|
|
.datac(!\A[0]~input_o ),
|
|
.datad(gnd),
|
|
.datae(!\op[0]~input_o ),
|
|
.dataf(!\op[1]~input_o ),
|
|
.datag(gnd),
|
|
.cin(gnd),
|
|
.sharein(gnd),
|
|
.combout(\Mux3~0_combout ),
|
|
.sumout(),
|
|
.cout(),
|
|
.shareout());
|
|
// synopsys translate_off
|
|
defparam \Mux3~0 .extended_lut = "off";
|
|
defparam \Mux3~0 .lut_mask = 64'h03033F3F3C3CC0C0;
|
|
defparam \Mux3~0 .shared_arith = "off";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X36_Y0_N52
|
|
cyclonev_io_ibuf \A[1]~input (
|
|
.i(A[1]),
|
|
.ibar(gnd),
|
|
.dynamicterminationcontrol(gnd),
|
|
.o(\A[1]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \A[1]~input .bus_hold = "false";
|
|
defparam \A[1]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X12_Y0_N35
|
|
cyclonev_io_ibuf \B[1]~input (
|
|
.i(B[1]),
|
|
.ibar(gnd),
|
|
.dynamicterminationcontrol(gnd),
|
|
.o(\B[1]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \B[1]~input .bus_hold = "false";
|
|
defparam \B[1]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: LABCELL_X17_Y1_N9
|
|
cyclonev_lcell_comb \Mux2~0 (
|
|
// Equation(s):
|
|
// \Mux2~0_combout = ( \op[0]~input_o & ( \op[1]~input_o & ( (!\A[1]~input_o & !\B[1]~input_o ) ) ) ) # ( !\op[0]~input_o & ( \op[1]~input_o & ( !\A[1]~input_o $ (!\B[1]~input_o ) ) ) ) # ( \op[0]~input_o & ( !\op[1]~input_o & ( (\B[1]~input_o ) #
|
|
// (\A[1]~input_o ) ) ) ) # ( !\op[0]~input_o & ( !\op[1]~input_o & ( (\A[1]~input_o & \B[1]~input_o ) ) ) )
|
|
|
|
.dataa(gnd),
|
|
.datab(!\A[1]~input_o ),
|
|
.datac(!\B[1]~input_o ),
|
|
.datad(gnd),
|
|
.datae(!\op[0]~input_o ),
|
|
.dataf(!\op[1]~input_o ),
|
|
.datag(gnd),
|
|
.cin(gnd),
|
|
.sharein(gnd),
|
|
.combout(\Mux2~0_combout ),
|
|
.sumout(),
|
|
.cout(),
|
|
.shareout());
|
|
// synopsys translate_off
|
|
defparam \Mux2~0 .extended_lut = "off";
|
|
defparam \Mux2~0 .lut_mask = 64'h03033F3F3C3CC0C0;
|
|
defparam \Mux2~0 .shared_arith = "off";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X17_Y0_N75
|
|
cyclonev_io_ibuf \B[2]~input (
|
|
.i(B[2]),
|
|
.ibar(gnd),
|
|
.dynamicterminationcontrol(gnd),
|
|
.o(\B[2]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \B[2]~input .bus_hold = "false";
|
|
defparam \B[2]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X34_Y0_N35
|
|
cyclonev_io_ibuf \A[2]~input (
|
|
.i(A[2]),
|
|
.ibar(gnd),
|
|
.dynamicterminationcontrol(gnd),
|
|
.o(\A[2]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \A[2]~input .bus_hold = "false";
|
|
defparam \A[2]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: LABCELL_X17_Y1_N15
|
|
cyclonev_lcell_comb \Mux1~0 (
|
|
// Equation(s):
|
|
// \Mux1~0_combout = ( \op[0]~input_o & ( \op[1]~input_o & ( (!\B[2]~input_o & !\A[2]~input_o ) ) ) ) # ( !\op[0]~input_o & ( \op[1]~input_o & ( !\B[2]~input_o $ (!\A[2]~input_o ) ) ) ) # ( \op[0]~input_o & ( !\op[1]~input_o & ( (\A[2]~input_o ) #
|
|
// (\B[2]~input_o ) ) ) ) # ( !\op[0]~input_o & ( !\op[1]~input_o & ( (\B[2]~input_o & \A[2]~input_o ) ) ) )
|
|
|
|
.dataa(!\B[2]~input_o ),
|
|
.datab(gnd),
|
|
.datac(!\A[2]~input_o ),
|
|
.datad(gnd),
|
|
.datae(!\op[0]~input_o ),
|
|
.dataf(!\op[1]~input_o ),
|
|
.datag(gnd),
|
|
.cin(gnd),
|
|
.sharein(gnd),
|
|
.combout(\Mux1~0_combout ),
|
|
.sumout(),
|
|
.cout(),
|
|
.shareout());
|
|
// synopsys translate_off
|
|
defparam \Mux1~0 .extended_lut = "off";
|
|
defparam \Mux1~0 .lut_mask = 64'h05055F5F5A5AA0A0;
|
|
defparam \Mux1~0 .shared_arith = "off";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X14_Y0_N52
|
|
cyclonev_io_ibuf \A[3]~input (
|
|
.i(A[3]),
|
|
.ibar(gnd),
|
|
.dynamicterminationcontrol(gnd),
|
|
.o(\A[3]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \A[3]~input .bus_hold = "false";
|
|
defparam \A[3]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X12_Y0_N52
|
|
cyclonev_io_ibuf \B[3]~input (
|
|
.i(B[3]),
|
|
.ibar(gnd),
|
|
.dynamicterminationcontrol(gnd),
|
|
.o(\B[3]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \B[3]~input .bus_hold = "false";
|
|
defparam \B[3]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: LABCELL_X17_Y1_N48
|
|
cyclonev_lcell_comb \Mux0~0 (
|
|
// Equation(s):
|
|
// \Mux0~0_combout = ( \op[0]~input_o & ( \op[1]~input_o & ( (!\A[3]~input_o & !\B[3]~input_o ) ) ) ) # ( !\op[0]~input_o & ( \op[1]~input_o & ( !\A[3]~input_o $ (!\B[3]~input_o ) ) ) ) # ( \op[0]~input_o & ( !\op[1]~input_o & ( (\B[3]~input_o ) #
|
|
// (\A[3]~input_o ) ) ) ) # ( !\op[0]~input_o & ( !\op[1]~input_o & ( (\A[3]~input_o & \B[3]~input_o ) ) ) )
|
|
|
|
.dataa(!\A[3]~input_o ),
|
|
.datab(gnd),
|
|
.datac(!\B[3]~input_o ),
|
|
.datad(gnd),
|
|
.datae(!\op[0]~input_o ),
|
|
.dataf(!\op[1]~input_o ),
|
|
.datag(gnd),
|
|
.cin(gnd),
|
|
.sharein(gnd),
|
|
.combout(\Mux0~0_combout ),
|
|
.sumout(),
|
|
.cout(),
|
|
.shareout());
|
|
// synopsys translate_off
|
|
defparam \Mux0~0 .extended_lut = "off";
|
|
defparam \Mux0~0 .lut_mask = 64'h05055F5F5A5AA0A0;
|
|
defparam \Mux0~0 .shared_arith = "off";
|
|
// synopsys translate_on
|
|
|
|
// Location: LABCELL_X48_Y45_N0
|
|
cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
|
|
// Equation(s):
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(gnd),
|
|
.datae(gnd),
|
|
.dataf(gnd),
|
|
.datag(gnd),
|
|
.cin(gnd),
|
|
.sharein(gnd),
|
|
.combout(\~QUARTUS_CREATED_GND~I_combout ),
|
|
.sumout(),
|
|
.cout(),
|
|
.shareout());
|
|
// synopsys translate_off
|
|
defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
|
|
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
|
|
defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
|
|
// synopsys translate_on
|
|
|
|
endmodule
|