473 lines
13 KiB
Plaintext
473 lines
13 KiB
Plaintext
// Copyright (C) 2025 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and any partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, the Altera Quartus Prime License Agreement,
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// the Altera IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Altera and sold by Altera or its authorized distributors. Please
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// refer to the Altera Software License Subscription Agreements
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// on the Quartus Prime software download page.
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// VENDOR "Altera"
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// PROGRAM "Quartus Prime"
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// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
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// DATE "09/10/2026 14:02:02"
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//
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// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
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//
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//
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// This Verilog file should be used for Questa Altera FPGA (SystemVerilog) only
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//
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`timescale 1 ps/ 1 ps
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module asu (
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op,
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A,
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B,
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OUT_1,
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COUT,
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OUT_CIN);
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input [0:0] op;
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input [3:0] A;
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input [3:0] B;
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output [3:0] OUT_1;
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output [0:0] COUT;
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output [0:0] OUT_CIN;
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// Design Ports Information
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// OUT_1[0] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default
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// OUT_1[1] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default
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// OUT_1[2] => Location: PIN_G6, I/O Standard: 2.5 V, Current Strength: Default
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// OUT_1[3] => Location: PIN_G7, I/O Standard: 2.5 V, Current Strength: Default
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// COUT[0] => Location: PIN_J8, I/O Standard: 2.5 V, Current Strength: Default
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// OUT_CIN[0] => Location: PIN_L7, I/O Standard: 2.5 V, Current Strength: Default
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// op[0] => Location: PIN_AE19, I/O Standard: 1.2 V, Current Strength: Default
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// A[3] => Location: PIN_AC8, I/O Standard: 1.2 V, Current Strength: Default
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// B[3] => Location: PIN_AC10, I/O Standard: 1.2 V, Current Strength: Default
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// B[0] => Location: PIN_W11, I/O Standard: 1.2 V, Current Strength: Default
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// A[0] => Location: PIN_AC9, I/O Standard: 1.2 V, Current Strength: Default
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// A[1] => Location: PIN_AE10, I/O Standard: 1.2 V, Current Strength: Default
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// B[1] => Location: PIN_AB10, I/O Standard: 1.2 V, Current Strength: Default
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// A[2] => Location: PIN_AD13, I/O Standard: 1.2 V, Current Strength: Default
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// B[2] => Location: PIN_V10, I/O Standard: 1.2 V, Current Strength: Default
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wire gnd;
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wire vcc;
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wire unknown;
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assign gnd = 1'b0;
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assign vcc = 1'b1;
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assign unknown = 1'bx;
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tri1 devclrn;
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tri1 devpor;
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tri1 devoe;
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wire \~QUARTUS_CREATED_GND~I_combout ;
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wire \op[0]~input_o ;
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wire \A[0]~input_o ;
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wire \B[0]~input_o ;
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wire \_~1_sumout ;
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wire \A[1]~input_o ;
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wire \B[1]~input_o ;
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wire \_~2 ;
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wire \_~3 ;
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wire \_~5_sumout ;
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wire \A[2]~input_o ;
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wire \B[2]~input_o ;
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wire \_~6 ;
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wire \_~7 ;
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wire \_~9_sumout ;
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wire \A[3]~input_o ;
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wire \B[3]~input_o ;
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wire \_~10 ;
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wire \_~11 ;
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wire \_~13_sumout ;
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wire \_~14 ;
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wire \_~15 ;
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wire \_~17_sumout ;
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wire \OUT_CIN~0_combout ;
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// Location: IOOBUF_X14_Y61_N53
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cyclonev_io_obuf \OUT_1[0]~output (
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.i(\_~1_sumout ),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(OUT_1[0]),
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.obar());
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// synopsys translate_off
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defparam \OUT_1[0]~output .bus_hold = "false";
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defparam \OUT_1[0]~output .open_drain_output = "false";
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defparam \OUT_1[0]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X15_Y61_N36
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cyclonev_io_obuf \OUT_1[1]~output (
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.i(\_~5_sumout ),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(OUT_1[1]),
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.obar());
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// synopsys translate_off
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defparam \OUT_1[1]~output .bus_hold = "false";
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defparam \OUT_1[1]~output .open_drain_output = "false";
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defparam \OUT_1[1]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X15_Y61_N53
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cyclonev_io_obuf \OUT_1[2]~output (
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.i(\_~9_sumout ),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(OUT_1[2]),
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.obar());
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// synopsys translate_off
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defparam \OUT_1[2]~output .bus_hold = "false";
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defparam \OUT_1[2]~output .open_drain_output = "false";
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defparam \OUT_1[2]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X14_Y61_N36
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cyclonev_io_obuf \OUT_1[3]~output (
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.i(\_~13_sumout ),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(OUT_1[3]),
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.obar());
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// synopsys translate_off
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defparam \OUT_1[3]~output .bus_hold = "false";
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defparam \OUT_1[3]~output .open_drain_output = "false";
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defparam \OUT_1[3]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X14_Y61_N19
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cyclonev_io_obuf \COUT[0]~output (
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.i(\_~17_sumout ),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(COUT[0]),
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.obar());
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// synopsys translate_off
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defparam \COUT[0]~output .bus_hold = "false";
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defparam \COUT[0]~output .open_drain_output = "false";
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defparam \COUT[0]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X10_Y61_N42
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cyclonev_io_obuf \OUT_CIN[0]~output (
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.i(\OUT_CIN~0_combout ),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(OUT_CIN[0]),
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.obar());
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// synopsys translate_off
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defparam \OUT_CIN[0]~output .bus_hold = "false";
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defparam \OUT_CIN[0]~output .open_drain_output = "false";
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defparam \OUT_CIN[0]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOIBUF_X50_Y0_N35
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cyclonev_io_ibuf \op[0]~input (
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.i(op[0]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\op[0]~input_o ));
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// synopsys translate_off
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defparam \op[0]~input .bus_hold = "false";
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defparam \op[0]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X14_Y0_N35
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cyclonev_io_ibuf \A[0]~input (
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.i(A[0]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\A[0]~input_o ));
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// synopsys translate_off
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defparam \A[0]~input .bus_hold = "false";
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defparam \A[0]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X10_Y0_N41
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cyclonev_io_ibuf \B[0]~input (
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.i(B[0]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\B[0]~input_o ));
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// synopsys translate_off
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defparam \B[0]~input .bus_hold = "false";
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defparam \B[0]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LABCELL_X18_Y4_N30
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cyclonev_lcell_comb \_~1 (
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// Equation(s):
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// \_~1_sumout = SUM(( !\A[0]~input_o $ (!\B[0]~input_o ) ) + ( !VCC ) + ( !VCC ))
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// \_~2 = CARRY(( !\A[0]~input_o $ (!\B[0]~input_o ) ) + ( !VCC ) + ( !VCC ))
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// \_~3 = SHARE((!\B[0]~input_o & (\op[0]~input_o )) # (\B[0]~input_o & ((\A[0]~input_o ))))
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.dataa(gnd),
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.datab(!\op[0]~input_o ),
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.datac(!\A[0]~input_o ),
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.datad(!\B[0]~input_o ),
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.datae(gnd),
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.dataf(gnd),
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.datag(gnd),
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.cin(gnd),
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.sharein(gnd),
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.combout(),
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.sumout(\_~1_sumout ),
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.cout(\_~2 ),
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.shareout(\_~3 ));
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// synopsys translate_off
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defparam \_~1 .extended_lut = "off";
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defparam \_~1 .lut_mask = 64'h0000330F00000FF0;
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defparam \_~1 .shared_arith = "on";
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// synopsys translate_on
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// Location: IOIBUF_X36_Y0_N52
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cyclonev_io_ibuf \A[1]~input (
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.i(A[1]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\A[1]~input_o ));
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// synopsys translate_off
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defparam \A[1]~input .bus_hold = "false";
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defparam \A[1]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X12_Y0_N35
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cyclonev_io_ibuf \B[1]~input (
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.i(B[1]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\B[1]~input_o ));
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// synopsys translate_off
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defparam \B[1]~input .bus_hold = "false";
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defparam \B[1]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LABCELL_X18_Y4_N33
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cyclonev_lcell_comb \_~5 (
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// Equation(s):
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// \_~5_sumout = SUM(( !\A[1]~input_o $ (!\op[0]~input_o $ (\B[1]~input_o )) ) + ( \_~3 ) + ( \_~2 ))
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// \_~6 = CARRY(( !\A[1]~input_o $ (!\op[0]~input_o $ (\B[1]~input_o )) ) + ( \_~3 ) + ( \_~2 ))
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// \_~7 = SHARE((\A[1]~input_o & (!\op[0]~input_o $ (!\B[1]~input_o ))))
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.dataa(!\A[1]~input_o ),
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.datab(!\op[0]~input_o ),
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.datac(!\B[1]~input_o ),
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.datad(gnd),
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.datae(gnd),
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.dataf(gnd),
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.datag(gnd),
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.cin(\_~2 ),
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.sharein(\_~3 ),
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.combout(),
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.sumout(\_~5_sumout ),
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.cout(\_~6 ),
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.shareout(\_~7 ));
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// synopsys translate_off
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defparam \_~5 .extended_lut = "off";
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defparam \_~5 .lut_mask = 64'h0000141400006969;
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defparam \_~5 .shared_arith = "on";
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// synopsys translate_on
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// Location: IOIBUF_X34_Y0_N35
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cyclonev_io_ibuf \A[2]~input (
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.i(A[2]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\A[2]~input_o ));
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// synopsys translate_off
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defparam \A[2]~input .bus_hold = "false";
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defparam \A[2]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X17_Y0_N75
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cyclonev_io_ibuf \B[2]~input (
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.i(B[2]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\B[2]~input_o ));
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// synopsys translate_off
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defparam \B[2]~input .bus_hold = "false";
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defparam \B[2]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LABCELL_X18_Y4_N36
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cyclonev_lcell_comb \_~9 (
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// Equation(s):
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// \_~9_sumout = SUM(( !\op[0]~input_o $ (!\A[2]~input_o $ (\B[2]~input_o )) ) + ( \_~7 ) + ( \_~6 ))
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// \_~10 = CARRY(( !\op[0]~input_o $ (!\A[2]~input_o $ (\B[2]~input_o )) ) + ( \_~7 ) + ( \_~6 ))
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// \_~11 = SHARE((\A[2]~input_o & (!\op[0]~input_o $ (!\B[2]~input_o ))))
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.dataa(gnd),
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.datab(!\op[0]~input_o ),
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.datac(!\A[2]~input_o ),
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.datad(!\B[2]~input_o ),
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.datae(gnd),
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.dataf(gnd),
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.datag(gnd),
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.cin(\_~6 ),
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.sharein(\_~7 ),
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.combout(),
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.sumout(\_~9_sumout ),
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.cout(\_~10 ),
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.shareout(\_~11 ));
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// synopsys translate_off
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defparam \_~9 .extended_lut = "off";
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defparam \_~9 .lut_mask = 64'h0000030C00003CC3;
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defparam \_~9 .shared_arith = "on";
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// synopsys translate_on
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// Location: IOIBUF_X14_Y0_N52
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cyclonev_io_ibuf \A[3]~input (
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.i(A[3]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\A[3]~input_o ));
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// synopsys translate_off
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defparam \A[3]~input .bus_hold = "false";
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defparam \A[3]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X12_Y0_N52
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cyclonev_io_ibuf \B[3]~input (
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.i(B[3]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\B[3]~input_o ));
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// synopsys translate_off
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defparam \B[3]~input .bus_hold = "false";
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defparam \B[3]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LABCELL_X18_Y4_N39
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cyclonev_lcell_comb \_~13 (
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// Equation(s):
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// \_~13_sumout = SUM(( !\op[0]~input_o $ (!\A[3]~input_o $ (\B[3]~input_o )) ) + ( \_~11 ) + ( \_~10 ))
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// \_~14 = CARRY(( !\op[0]~input_o $ (!\A[3]~input_o $ (\B[3]~input_o )) ) + ( \_~11 ) + ( \_~10 ))
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// \_~15 = SHARE((\A[3]~input_o & (!\op[0]~input_o $ (!\B[3]~input_o ))))
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.dataa(gnd),
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.datab(!\op[0]~input_o ),
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.datac(!\A[3]~input_o ),
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.datad(!\B[3]~input_o ),
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.datae(gnd),
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.dataf(gnd),
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.datag(gnd),
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.cin(\_~10 ),
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.sharein(\_~11 ),
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.combout(),
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.sumout(\_~13_sumout ),
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.cout(\_~14 ),
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.shareout(\_~15 ));
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// synopsys translate_off
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defparam \_~13 .extended_lut = "off";
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defparam \_~13 .lut_mask = 64'h0000030C00003CC3;
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defparam \_~13 .shared_arith = "on";
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// synopsys translate_on
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// Location: LABCELL_X18_Y4_N42
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cyclonev_lcell_comb \_~17 (
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// Equation(s):
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// \_~17_sumout = SUM(( GND ) + ( \_~15 ) + ( \_~14 ))
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.dataa(gnd),
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.datab(gnd),
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.datac(gnd),
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.datad(gnd),
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.datae(gnd),
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.dataf(gnd),
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.datag(gnd),
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.cin(\_~14 ),
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.sharein(\_~15 ),
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.combout(),
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.sumout(\_~17_sumout ),
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.cout(),
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.shareout());
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// synopsys translate_off
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defparam \_~17 .extended_lut = "off";
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defparam \_~17 .lut_mask = 64'h0000000000000000;
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defparam \_~17 .shared_arith = "on";
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// synopsys translate_on
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// Location: LABCELL_X18_Y4_N0
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cyclonev_lcell_comb \OUT_CIN~0 (
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// Equation(s):
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// \OUT_CIN~0_combout = ( \B[3]~input_o & ( \op[0]~input_o & ( !\_~13_sumout $ (!\A[3]~input_o ) ) ) ) # ( !\B[3]~input_o & ( \op[0]~input_o & ( !\_~13_sumout $ (\A[3]~input_o ) ) ) ) # ( \B[3]~input_o & ( !\op[0]~input_o & ( !\_~13_sumout $
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// (\A[3]~input_o ) ) ) ) # ( !\B[3]~input_o & ( !\op[0]~input_o & ( !\_~13_sumout $ (!\A[3]~input_o ) ) ) )
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.dataa(gnd),
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.datab(!\_~13_sumout ),
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.datac(gnd),
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.datad(!\A[3]~input_o ),
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.datae(!\B[3]~input_o ),
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.dataf(!\op[0]~input_o ),
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.datag(gnd),
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.cin(gnd),
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.sharein(gnd),
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.combout(\OUT_CIN~0_combout ),
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.sumout(),
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.cout(),
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.shareout());
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// synopsys translate_off
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defparam \OUT_CIN~0 .extended_lut = "off";
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defparam \OUT_CIN~0 .lut_mask = 64'h33CCCC33CC3333CC;
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defparam \OUT_CIN~0 .shared_arith = "off";
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// synopsys translate_on
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// Location: MLABCELL_X42_Y27_N0
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cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
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// Equation(s):
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.dataa(gnd),
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.datab(gnd),
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.datac(gnd),
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.datad(gnd),
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.datae(gnd),
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.dataf(gnd),
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.datag(gnd),
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.cin(gnd),
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.sharein(gnd),
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.combout(\~QUARTUS_CREATED_GND~I_combout ),
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.sumout(),
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.cout(),
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.shareout());
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// synopsys translate_off
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defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
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defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
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defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
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// synopsys translate_on
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endmodule
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