`ifndef REGISTER_FILE_H
`define REGISTER_FILE_H

module register_file #(parameter width=5, parameter nregs=16)(
    input logic [0:0] clk, input logic[0:0] we,
    input logic [$clog(nregs)-1:0] A_W1, input logic [2**width-1:0] W1,
    input logic [$clog(nregs)-1:0] A_R1, output logic [2**width-1:0] R1,
    input logic [$clog(nregs)-1:0] A_R2, output logic [2**width-1:0] R2
);
    localparam BW = 2**width;
    logic [2**width-1:0] regs[nregs];

    always_ff @(posedge clk) begin
        if (we & (A_W1 != {(2**width){1'b0}} )) begin
            regs[A_W1] <= W1;
        end
    end

    assign R1 = regs[A_R1];
    assign R2 = regs[A_R2];
endmodule
`endif