12 lines
373 B
Verilog
12 lines
373 B
Verilog
module lu #(width=8) (
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input logic [1:0] op,
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input logic [width-1:0] A, input logic [width-1:0] B,
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output logic [width-1:0] OUT_1);
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always_comb begin
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if (op == 2'b00) OUT_1 = A & B;
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else if (op == 2'b01) OUT_1 = A | B;
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else if (op == 2'b10) OUT_1 = A ^ B;
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else if (op == 2'b10) OUT_1 = ~(A | B);
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end
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endmodule |