TroubleElectrical/FPGA_Uni
1
0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
Files
0947f26727ac8d9b86196bd9a8dccfce0ce50862
FPGA_Uni/Quartus/A1_Q3/simulation/questa/asu.sft
T

2 lines
51 B
Plaintext
Raw Blame History

set tool_name "Questa Altera FPGA (SystemVerilog)"
Reference in new issue View Git Blame Copy Permalink